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minor rtl edits and cleanups #679

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Sep 1, 2023
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minor rtl edits and cleanups #679

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157c1e8
[rtl] minor comment edits
stnolting Sep 1, 2023
28fd5ff
[rtl] minor edits/cleanups
stnolting Sep 1, 2023
6c8275b
[CHANGELOG] add v 1.8.8.6
stnolting Sep 1, 2023
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date (*dd.mm.yyyy*) | Version | Comment |
|:-------------------:|:-------:|:--------|
| 01.09.2023 | 1.8.8.6 | minor rtl edits and cleanups; [#679](https://github.com/stnolting/neorv32/pull/679) |
| 30.08.2023 | 1.8.8.5 | remove "branch prediction" logic - core is smaller and _even faster_ without it; [#678](https://github.com/stnolting/neorv32/pull/678) |
| 25.08.2023 | 1.8.8.4 | add new generic to downgrade on-chip debugger's debug module back to spec. version 0.13 (`DM_LEGACY_MODE` generic); [#677](https://github.com/stnolting/neorv32/pull/677) |
| 23.08.2023 | 1.8.8.3 | :test_tube: add experimental `Smcntrpmf` ISA extension (counter privilege mode filtering; spec. is frozen but not yet ratified); remove unused `menvcfg` CSRs; [#676](https://github.com/stnolting/neorv32/pull/676) |
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2 changes: 1 addition & 1 deletion rtl/core/neorv32_cpu.vhd
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Expand Up @@ -368,7 +368,7 @@ begin
addr_i => alu_add, -- access address
wdata_i => rs2, -- write data
rdata_o => mem_rdata, -- read data
mar_o => mar, -- current memory address register
mar_o => mar, -- memory address register
d_wait_o => bus_d_wait, -- wait for access to complete
ma_load_o => ma_load, -- misaligned load data address
ma_store_o => ma_store, -- misaligned store data address
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46 changes: 26 additions & 20 deletions rtl/core/neorv32_cpu_alu.vhd
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Expand Up @@ -100,6 +100,9 @@ architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
signal cp_start : std_ulogic_vector(4 downto 0); -- co-processor trigger
signal cp_valid : std_ulogic_vector(4 downto 0); -- co-processor done

-- CSR read-backs --
signal csr_rdata_fpu : std_ulogic_vector(XLEN-1 downto 0);

begin

-- Comparator Unit (for conditional branches) ---------------------------------------------
Expand All @@ -117,12 +120,12 @@ begin
opa <= pc_i when (ctrl_i.alu_opa_mux = '1') else rs1_i;
opb <= imm_i when (ctrl_i.alu_opb_mux = '1') else rs2_i;

opa_x <= (opa(opa'left) and (not ctrl_i.alu_unsigned)) & opa; -- sign-extend
opb_x <= (opb(opb'left) and (not ctrl_i.alu_unsigned)) & opb; -- sign-extend


-- Adder/Subtracter Core ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
opa_x <= (opa(opa'left) and (not ctrl_i.alu_unsigned)) & opa; -- sign-extend
opb_x <= (opb(opb'left) and (not ctrl_i.alu_unsigned)) & opb; -- sign-extend

addsub_res <= std_ulogic_vector(unsigned(opa_x) - unsigned(opb_x)) when (ctrl_i.alu_op(0) = '1') else
std_ulogic_vector(unsigned(opa_x) + unsigned(opb_x));

Expand Down Expand Up @@ -163,6 +166,9 @@ begin
-- > "cp_result" data has to be always zero unless the specific co-processor has been actually triggered
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3) or cp_result(4);

-- co-processor CSR read-back --
csr_rdata_o <= csr_rdata_fpu;


-- Co-Processor 0: Shifter Unit (Base ISA) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
Expand Down Expand Up @@ -255,31 +261,31 @@ begin
neorv32_cpu_cp_fpu_inst: entity neorv32.neorv32_cpu_cp_fpu
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl_i, -- main control bus
start_i => cp_start(3), -- trigger operation
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
ctrl_i => ctrl_i, -- main control bus
start_i => cp_start(3), -- trigger operation
-- CSR interface --
csr_we_i => csr_we_i, -- global write enable
csr_addr_i => csr_addr_i, -- address
csr_wdata_i => csr_wdata_i, -- write data
csr_rdata_o => csr_rdata_o, -- read data
csr_we_i => csr_we_i, -- global write enable
csr_addr_i => csr_addr_i, -- address
csr_wdata_i => csr_wdata_i, -- write data
csr_rdata_o => csr_rdata_fpu, -- read data
-- data input --
cmp_i => cmp, -- comparator status
rs1_i => rs1_i, -- rf source 1
rs2_i => rs2_i, -- rf source 2
rs3_i => rs3_i, -- rf source 3
cmp_i => cmp, -- comparator status
rs1_i => rs1_i, -- rf source 1
rs2_i => rs2_i, -- rf source 2
rs3_i => rs3_i, -- rf source 3
-- result and status --
res_o => cp_result(3), -- operation result
valid_o => cp_valid(3) -- data output valid
res_o => cp_result(3), -- operation result
valid_o => cp_valid(3) -- data output valid
);
end generate;

neorv32_cpu_cp_fpu_inst_false:
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
csr_rdata_o <= (others => '0');
cp_result(3) <= (others => '0');
cp_valid(3) <= '0';
csr_rdata_fpu <= (others => '0');
cp_result(3) <= (others => '0');
cp_valid(3) <= '0';
end generate;


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