⚠️ rework SoC bus protocol #697
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stnolting
added
HW
still quite experimental!
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This PR is a rework of the processor-internal bus system to make it more Wishbone-alike. The individual request signals
reandweare replaced by a single request strobe (stb) and a read/write identifier (rw). This allows to simplify (in terms of hardware resources) the CPU's load-store unit as well as all the bus elements (muxes) as a only a single request signal needs to be evaluated.Pre-PR Protocol
Post-PR Protocol