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set top entiy input defaults to 'L' or 'H' #779

Merged
merged 2 commits into from
Jan 29, 2024
Merged

set top entiy input defaults to 'L' or 'H' #779

merged 2 commits into from
Jan 29, 2024

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stnolting
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@stnolting stnolting commented Jan 29, 2024

using VHDL's "weak driver strengths" to model a pull-down / pull-up "resistor" in case these signals are not explicitly assigned during instantiation

modeling a pull-down / pull-up "resistor" in case these signals are not explicitly assigned during instantiation
@stnolting stnolting added the HW Hardware-related label Jan 29, 2024
@stnolting stnolting self-assigned this Jan 29, 2024
@stnolting stnolting marked this pull request as ready for review January 29, 2024 17:08
@stnolting stnolting merged commit 1e5811e into main Jan 29, 2024
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@stnolting stnolting deleted the dev290124 branch January 29, 2024 18:36
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