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[fifo] fix (Vivado) synthesis issue #827

Merged
merged 3 commits into from
Feb 23, 2024
Merged

[fifo] fix (Vivado) synthesis issue #827

merged 3 commits into from
Feb 23, 2024

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stnolting
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Vivado was not able to infer block RAM / LUT-RAM for the FIFO memory.

@robhancocksed, @mikaelsky, @umarcor

Vivado was not able to infer block RAM / LUT-RAM for the FIFO memory
@stnolting stnolting added HW Hardware-related optimization Make things faster, smaller and more efficient labels Feb 23, 2024
@stnolting stnolting self-assigned this Feb 23, 2024
@stnolting stnolting linked an issue Feb 23, 2024 that may be closed by this pull request
not required, but helps to make the actual configuration clearer
@stnolting stnolting marked this pull request as ready for review February 23, 2024 06:57
@stnolting stnolting merged commit 53930a6 into main Feb 23, 2024
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@stnolting stnolting deleted the fifo_syn_fix branch February 23, 2024 09:35
@robhancocksed
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I can confirm that Vivado is now inferring the CPU prefetch buffer, SLINK and UART FIFOs as RAM rather than registers (though in this case distributed RAM rather than block RAM, since they are set to be quite small).

@stnolting
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I can confirm that Vivado is now inferring the CPU prefetch buffer, SLINK and UART FIFOs as RAM rather than registers (though in this case distributed RAM rather than block RAM, since they are set to be quite small).

Great to hear!

Thanks for the feedback!

@umarcor
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umarcor commented Feb 24, 2024

I can also confirm that I can now get expected results (#753 (comment)) with the main branch. I merged stnolting/neorv32-setups#150 for neorv32-setups to pick recent changes and then implementation suceeded without further modifications.

@stnolting
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Thanks @umarcor! 👍

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neorv32_fifo vivado implementation issue
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