[fifo] fix (Vivado) synthesis issue

[stnolting]

Vivado was not able to infer block RAM / LUT-RAM for the FIFO memory.

@robhancocksed, @mikaelsky, @umarcor

[robhancocksed]

I can confirm that Vivado is now inferring the CPU prefetch buffer, SLINK and UART FIFOs as RAM rather than registers (though in this case distributed RAM rather than block RAM, since they are set to be quite small).

[stnolting]

I can confirm that Vivado is now inferring the CPU prefetch buffer, SLINK and UART FIFOs as RAM rather than registers (though in this case distributed RAM rather than block RAM, since they are set to be quite small).

Great to hear!

Thanks for the feedback!

[umarcor]

I can also confirm that I can now get expected results (#753 (comment)) with the main branch. I merged stnolting/neorv32-setups#150 for neorv32-setups to pick recent changes and then implementation suceeded without further modifications.

[stnolting]

Thanks @umarcor! 👍