optimize FIFO component to improve mapping

[stnolting]

When configured as "async read" FIFO an additional register (r_pnt_ff) for the read pointer / read address is added. This allows to map the FIFO memory to FPGA blockRAM while preserving the "asynchronous" read behavior.

-- more than 1 FIFO entries --
fifo_read_async_large:
if (fifo_depth_c > 1) generate
  async_r_pnt_reg: process(clk_i)
  begin
    if rising_edge(clk_i) then
      r_pnt_ff <= r_nxt; -- individual read address register; allows mapping "async" FIFOs to memory primitives
    end if;
  end process async_r_pnt_reg;
  rdata_o <= fifo_mem(to_integer(unsigned(r_pnt_ff(r_pnt_ff'left-1 downto 0))));
end generate;

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🐛 This PR also changes the SLINK FIFOs to "async read" mode trying to fix #826.