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rework cache system #853

Merged
merged 13 commits into from
Mar 17, 2024
Merged

rework cache system #853

merged 13 commits into from
Mar 17, 2024

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stnolting
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@stnolting stnolting commented Mar 16, 2024

This PR updates all the entire cache system of the processor. With this PR in place, we now have a total of 4 different caches (instances of neorv32_cache.vhd) organized in two levels:

  • L1 caches
    • CPU instruction cache (I-CACHE)
    • CPU data cache (D-CACHE)
  • L2 caches
    • execute in-place cache (XIP-CACHE)
    • external bus interface cache (X-CACHE)

Enabling all caches at the same time makes no sense. You should therefore either only activate the L2 caches or only the L1 caches. For configurations that mainly use the processor's internal memory, only the L2 caches should be used.

There is an ongoing discussion (#793) as to whether we should remove the L1 caches (i-cache & d-cache) completely. I am curious to hear what you think about this. 😉

neorv32_bus

Important

As the i-cache now also uses the generic cache module (which is direct-mapped) the ICACHE_ASSOCIATIVITY generic is removed. Furthermore, the cache-specific neorv32_icache.vhd and neorv32_dcache.vhd rtl files are removed.

@stnolting stnolting added the HW Hardware-related label Mar 16, 2024
@stnolting stnolting self-assigned this Mar 16, 2024
@stnolting stnolting marked this pull request as ready for review March 16, 2024 20:59
@stnolting stnolting merged commit 082146d into main Mar 17, 2024
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@stnolting stnolting deleted the cache_system branch March 17, 2024 19:32
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