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⚠️ rework ONEWIRE and GPTMR interrupts #859

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Mar 23, 2024
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⚠️ Rework ONEWIRE Interrupt

The interrupt of the ONEWIRE module will now become set whenever the module is in idle state (e.g. after completing an operation).

⚠️ Rework GPTMR Interrupt

The GPTMR timer interrupt will now remain pending until explicitly cleared by writing zero to the module's GPTMR_CTRL_TRIGM and/or GPTMR_CTRL_TRIGC control register bits (depneing on the interrupt trigger configuration).

Note

This PR is part of a series that aims to unify (and simplify) the entire interrupt system of the processor.

@stnolting stnolting added HW Hardware-related cleanup Clean-up the codebase labels Mar 23, 2024
@stnolting stnolting self-assigned this Mar 23, 2024
keep interrupt pending until explicitly cleared by writing zero to interrupt trigger state bit(s)
interrupt will stay active as long as the module is in idle state
@stnolting stnolting marked this pull request as ready for review March 23, 2024 20:52
@stnolting stnolting merged commit fe384b7 into main Mar 23, 2024
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@stnolting stnolting deleted the irq_rework_230324 branch March 23, 2024 20:58
@stnolting stnolting added the experimental Experimental feature label Mar 23, 2024
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