v1.9.5

What's Changed

• fix trap priority by @stnolting in #784
• Add support for page fault exceptions by @stnolting in #786
• [cpu] fix minor bug in instruction request bus by @stnolting in #790
• Fix for issue #785: FPU fflags no being asserted correctly by @mikaelsky in #788
• 🐛 [cpu] fix non-stable privilege signal of instruction interface by @stnolting in #792
• [CPU] close further illegal instruction loopholes by @stnolting in #797
• ✨ add optional XIP cache by @stnolting in #799
• add fence signal to CPU bus by @stnolting in #800
• 🐛 fix fence signal pass-through in caches by @stnolting in #802
• [rtl] fix HPM null range assertions by @stnolting in #803
• minor rtl edits by @stnolting in #804
• Fixes to the FPU for issue #791 by @mikaelsky in #794
• 🐛 fix another C-ISA loophole by @stnolting in #806
• Add DMA fence operation by @stnolting in #807

Full Changelog: v1.9.4...v1.9.5