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[RISCV] Add an instruction PrettyPrinter to llvm-objdump (llvm#90093)
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This prints the opcode bytes in the same order as GNU objdump without a
space between them.
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@topperc
topperc authored Apr 26, 2024
1 parent 760910d commit b27f86b
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16 changes: 8 additions & 8 deletions lld/test/ELF/riscv-branch.s
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Expand Up @@ -7,19 +7,19 @@
# RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64
# CHECK-32: 63 02 00 00 beqz zero, 0x110b8
# CHECK-32: e3 1e 00 fe bnez zero, 0x110b4
# CHECK-64: 63 02 00 00 beqz zero, 0x11124
# CHECK-64: e3 1e 00 fe bnez zero, 0x11120
# CHECK-32: 00000263 beqz zero, 0x110b8
# CHECK-32: fe001ee3 bnez zero, 0x110b4
# CHECK-64: 00000263 beqz zero, 0x11124
# CHECK-64: fe001ee3 bnez zero, 0x11120
#
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv32.limits
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv64.limits
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s
# LIMITS-32: e3 0f 00 7e beqz zero, 0x120b2
# LIMITS-32-NEXT: 63 10 00 80 bnez zero, 0x100b8
# LIMITS-64: e3 0f 00 7e beqz zero, 0x1211e
# LIMITS-64-NEXT: 63 10 00 80 bnez zero, 0x10124
# LIMITS-32: 7e000fe3 beqz zero, 0x120b2
# LIMITS-32-NEXT: 80001063 bnez zero, 0x100b8
# LIMITS-64: 7e000fe3 beqz zero, 0x1211e
# LIMITS-64-NEXT: 80001063 bnez zero, 0x10124

# RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
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16 changes: 8 additions & 8 deletions lld/test/ELF/riscv-call.s
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Expand Up @@ -7,19 +7,19 @@
# RUN: ld.lld %t.rv64.o --defsym foo=_start+8 --defsym bar=_start -o %t.rv64
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
# CHECK: 97 00 00 00 auipc ra, 0x0
# CHECK-NEXT: e7 80 80 00 jalr 0x8(ra)
# CHECK: 97 00 00 00 auipc ra, 0x0
# CHECK-NEXT: e7 80 80 ff jalr -0x8(ra)
# CHECK: 00000097 auipc ra, 0x0
# CHECK-NEXT: 008080e7 jalr 0x8(ra)
# CHECK: 00000097 auipc ra, 0x0
# CHECK-NEXT: ff8080e7 jalr -0x8(ra)

# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv32.limits
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv64.limits
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
# LIMITS: 97 f0 ff 7f auipc ra, 0x7ffff
# LIMITS-NEXT: e7 80 f0 7f jalr 0x7ff(ra)
# LIMITS-NEXT: 97 00 00 80 auipc ra, 0x80000
# LIMITS-NEXT: e7 80 00 80 jalr -0x800(ra)
# LIMITS: 7ffff097 auipc ra, 0x7ffff
# LIMITS-NEXT: 7ff080e7 jalr 0x7ff(ra)
# LIMITS-NEXT: 80000097 auipc ra, 0x80000
# LIMITS-NEXT: 800080e7 jalr -0x800(ra)

# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o %t
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o /dev/null 2>&1 | \
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24 changes: 12 additions & 12 deletions lld/test/ELF/riscv-hi20-lo12.s
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Expand Up @@ -7,23 +7,23 @@
# RUN: ld.lld %t.rv64.o --defsym foo=0 --defsym bar=42 -o %t.rv64
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
# CHECK: 37 05 00 00 lui a0, 0x0
# CHECK-NEXT: 13 05 05 00 mv a0, a0
# CHECK-NEXT: 23 20 a5 00 sw a0, 0x0(a0)
# CHECK-NEXT: b7 05 00 00 lui a1, 0x0
# CHECK-NEXT: 93 85 a5 02 addi a1, a1, 0x2a
# CHECK-NEXT: 23 a5 b5 02 sw a1, 0x2a(a1)
# CHECK: 00000537 lui a0, 0x0
# CHECK-NEXT: 00050513 mv a0, a0
# CHECK-NEXT: 00a52023 sw a0, 0x0(a0)
# CHECK-NEXT: 000005b7 lui a1, 0x0
# CHECK-NEXT: 02a58593 addi a1, a1, 0x2a
# CHECK-NEXT: 02b5a523 sw a1, 0x2a(a1)

# RUN: ld.lld %t.rv32.o --defsym foo=0x7ffff7ff --defsym bar=0x7ffff800 -o %t.rv32.limits
# RUN: ld.lld %t.rv64.o --defsym foo=0x7ffff7ff --defsym bar=0xffffffff7ffff800 -o %t.rv64.limits
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
# LIMITS: 37 f5 ff 7f lui a0, 0x7ffff
# LIMITS-NEXT: 13 05 f5 7f addi a0, a0, 0x7ff
# LIMITS-NEXT: a3 2f a5 7e sw a0, 0x7ff(a0)
# LIMITS-NEXT: b7 05 00 80 lui a1, 0x80000
# LIMITS-NEXT: 93 85 05 80 addi a1, a1, -0x800
# LIMITS-NEXT: 23 a0 b5 80 sw a1, -0x800(a1)
# LIMITS: 7ffff537 lui a0, 0x7ffff
# LIMITS-NEXT: 7ff50513 addi a0, a0, 0x7ff
# LIMITS-NEXT: 7ea52fa3 sw a0, 0x7ff(a0)
# LIMITS-NEXT: 800005b7 lui a1, 0x80000
# LIMITS-NEXT: 80058593 addi a1, a1, -0x800
# LIMITS-NEXT: 80b5a023 sw a1, -0x800(a1)

# RUN: not ld.lld %t.rv64.o --defsym foo=0x7ffff800 --defsym bar=0xffffffff7ffff7ff -o /dev/null 2>&1 | FileCheck --check-prefix ERROR %s
# ERROR: relocation R_RISCV_HI20 out of range: 524288 is not in [-524288, 524287]; references 'foo'
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16 changes: 8 additions & 8 deletions lld/test/ELF/riscv-jal.s
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Expand Up @@ -7,19 +7,19 @@
# RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64
# CHECK-32: 6f 00 40 00 j 0x110b8
# CHECK-32: ef f0 df ff jal 0x110b4
# CHECK-64: 6f 00 40 00 j 0x11124
# CHECK-64: ef f0 df ff jal 0x11120
# CHECK-32: 0040006f j 0x110b8
# CHECK-32: ffdff0ef jal 0x110b4
# CHECK-64: 0040006f j 0x11124
# CHECK-64: ffdff0ef jal 0x11120

# RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv32.limits
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv64.limits
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s
# LIMITS-32: 6f f0 ff 7f j 0x1110b2
# LIMITS-32-NEXT: ef 00 00 80 jal 0xfff110b8
# LIMITS-64: 6f f0 ff 7f j 0x11111e
# LIMITS-64-NEXT: ef 00 00 80 jal 0xfffffffffff11124
# LIMITS-32: 7ffff06f j 0x1110b2
# LIMITS-32-NEXT: 800000ef jal 0xfff110b8
# LIMITS-64: 7ffff06f j 0x11111e
# LIMITS-64-NEXT: 800000ef jal 0xfffffffffff11124

# RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
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2 changes: 2 additions & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -113,6 +113,8 @@ Changes to the RISC-V Backend
* The experimental Ssqosid extension is supported.
* Zacas is no longer experimental.
* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension.
* llvm-objdump now prints disassembled opcode bytes in groups of 2 or 4 bytes to
match GNU objdump. The bytes within the groups are in big endian order.

Changes to the WebAssembly Backend
----------------------------------
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28 changes: 14 additions & 14 deletions llvm/test/MC/RISCV/XTHeadVdot-valid.s
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Expand Up @@ -12,82 +12,82 @@ th.vmaqau.vv v8, v20, v4, v0.t
# CHECK-INST: th.vmaqau.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x88]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 4a 88 <unknown>
# CHECK-UNKNOWN: 884a640b <unknown>

th.vmaqau.vv v8, v20, v4
# CHECK-INST: th.vmaqau.vv v8, v20, v4
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x8a]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 4a 8a <unknown>
# CHECK-UNKNOWN: 8a4a640b <unknown>

th.vmaqau.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqau.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x8c]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 8c <unknown>
# CHECK-UNKNOWN: 8c45640b <unknown>

th.vmaqau.vx v8, a0, v4
# CHECK-INST: th.vmaqau.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x8e]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 8e <unknown>
# CHECK-UNKNOWN: 8e45640b <unknown>

th.vmaqa.vv v8, v20, v4, v0.t
# CHECK-INST: th.vmaqa.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x80]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 4a 80 <unknown>
# CHECK-UNKNOWN: 804a640b <unknown>

th.vmaqa.vv v8, v20, v4
# CHECK-INST: th.vmaqa.vv v8, v20, v4
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x82]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 4a 82 <unknown>
# CHECK-UNKNOWN: 824a640b <unknown>

th.vmaqa.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqa.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x84]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 84 <unknown>
# CHECK-UNKNOWN: 8445640b <unknown>

th.vmaqa.vx v8, a0, v4
# CHECK-INST: th.vmaqa.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x86]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 86 <unknown>
# CHECK-UNKNOWN: 8645640b <unknown>

th.vmaqasu.vv v8, v20, v4, v0.t
# CHECK-INST: th.vmaqasu.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x90]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 4a 90 <unknown>
# CHECK-UNKNOWN: 904a640b <unknown>

th.vmaqasu.vv v8, v20, v4
# CHECK-INST: th.vmaqasu.vv v8, v20, v4
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x92]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 4a 92 <unknown>
# CHECK-UNKNOWN: 924a640b <unknown>

th.vmaqasu.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqasu.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x94]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 94 <unknown>
# CHECK-UNKNOWN: 9445640b <unknown>

th.vmaqasu.vx v8, a0, v4
# CHECK-INST: th.vmaqasu.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x96]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 96 <unknown>
# CHECK-UNKNOWN: 9645640b <unknown>

th.vmaqaus.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqaus.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x9c]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 9c <unknown>
# CHECK-UNKNOWN: 9c45640b <unknown>

th.vmaqaus.vx v8, a0, v4
# CHECK-INST: th.vmaqaus.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x9e]
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 0b 64 45 9e <unknown>
# CHECK-UNKNOWN: 9e45640b <unknown>
8 changes: 4 additions & 4 deletions llvm/test/MC/RISCV/align.s
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Expand Up @@ -98,11 +98,11 @@ test:
# The behavior is the same as GNU assembler.
.p2align 4, 1
# RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xC
# RELAX-INST: 01 01
# RELAX-INST: 01 01
# RELAX-INST: 0101
# RELAX-INST: 0101
# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xE
# C-OR-ZCA-EXT-RELAX-INST: 01 01
# C-EXT-INST: 01 01
# C-OR-ZCA-EXT-RELAX-INST: 0101
# C-EXT-INST: 0101
ret
# NORELAX-RELOC-NOT: R_RISCV
# C-OR-ZCA-EXT-NORELAX-RELOC-NOT: R_RISCV
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2 changes: 1 addition & 1 deletion llvm/test/MC/RISCV/compress-cjal.s
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Expand Up @@ -11,7 +11,7 @@

# c.jal is an rv32 only instruction.
jal ra, 2046
# CHECK-BYTES: fd 2f
# CHECK-BYTES: 2ffd
# CHECK-ALIASOBJ: jal 0x7fe
# CHECK-ALIAS: jal 2046
# CHECK-INST: c.jal 2046
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8 changes: 4 additions & 4 deletions llvm/test/MC/RISCV/compress-rv32d.s
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Expand Up @@ -43,22 +43,22 @@
# Tests double precision floating point instructions available in rv32 and in rv64.

fld ft0, 64(sp)
# CHECK-BYTES: 06 20
# CHECK-BYTES: 2006
# CHECK-ALIAS: fld ft0, 64(sp)
# CHECK-INST: c.fldsp ft0, 64(sp)
# CHECK: # encoding: [0x06,0x20]
fsd ft0, 64(sp)
# CHECK-BYTES: 82 a0
# CHECK-BYTES: a082
# CHECK-ALIAS: fsd ft0, 64(sp)
# CHECK-INST: c.fsdsp ft0, 64(sp)
# CHECK: # encoding: [0x82,0xa0]
fld fs0, 248(s0)
# CHECK-BYTES: 60 3c
# CHECK-BYTES: 3c60
# CHECK-ALIAS: fld fs0, 248(s0)
# CHECK-INST: c.fld fs0, 248(s0)
# CHECK: # encoding: [0x60,0x3c]
fsd fs0, 248(s0)
# CHECK-BYTES: 60 bc
# CHECK-BYTES: bc60
# CHECK-ALIAS: fsd fs0, 248(s0)
# CHECK-INST: c.fsd fs0, 248(s0)
# CHECK: # encoding: [0x60,0xbc]
8 changes: 4 additions & 4 deletions llvm/test/MC/RISCV/compress-rv32f.s
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Expand Up @@ -21,22 +21,22 @@

# Instructions that are 32 bit only.
flw ft0, 124(sp)
# CHECK-BYTES: 76 70
# CHECK-BYTES: 7076
# CHECK-ALIAS: flw ft0, 124(sp)
# CHECK-INST: c.flwsp ft0, 124(sp)
# CHECK: # encoding: [0x76,0x70]
fsw ft0, 124(sp)
# CHECK-BYTES: 82 fe
# CHECK-BYTES: fe82
# CHECK-ALIAS: fsw ft0, 124(sp)
# CHECK-INST: c.fswsp ft0, 124(sp)
# CHECK: # encoding: [0x82,0xfe]
flw fs0, 124(s0)
# CHECK-BYTES: 60 7c
# CHECK-BYTES: 7c60
# CHECK-ALIAS: flw fs0, 124(s0)
# CHECK-INST: c.flw fs0, 124(s0)
# CHECK: # encoding: [0x60,0x7c]
fsw fs0, 124(s0)
# CHECK-BYTES: 60 fc
# CHECK-BYTES: fc60
# CHECK-ALIAS: fsw fs0, 124(s0)
# CHECK-INST: c.fsw fs0, 124(s0)
# CHECK: # encoding: [0x60,0xfc]
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