Awesome Hardware Description Languages

A curated list of amazingly awesome hardware description language projects.

Hardware developement

HDL doc

• Verilog IEEE Std 1364-2001, Quick Ref Guide, SystemVerilog 3.1a, Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification
• VHDL standards IEEE Std 1076-2000
• SystemC standards IEEE Std 1666-2011

HDL simulators and compilers

• Verilog
  • Verilator Verilog to C++ transpiler
  • Icarus Verilog - simulator
  • Yosys - RTL synthesis
• VHDL
  • nvc - GPLv3 VHDL compiler and simulator, IEEE 1076-2002, writen in C
  • GHDL - VHDL compiler and simulator, IEEE 1076-2002, writen in ADA
• Lola-2
  • Oberon-2013 - Project Oberon, 2013 Edition, written in Oberon-07 License

Meta HDL and Transpilers

• C++

  • VisualHDL - an integrated development environment (IDE) rapid design for FPGAs

• Haskell

  • concat Haskell to hardware, 2016+
  • https://github.com/conal/talk-2015-haskell-to-hardware
  • CλaSH - A functional hardware description language
  • pipelineDSL - A Haskell DSL for describing hardware pipelines

• Java

  • jhdl ..2006
  • PSHDL

• JavaScript

  • reqack - elastic circuit toolchain
  • hdl-js - Hardware description language (HDL) parser, and Hardware simulator.
  • shdl - Simple Hardware Description Language

• Julia

  • Julia-Verilog - a Verilog-generation DSL for Julia., 2017

• Python

  • HWT Meta HDL, verification env. IP-core generator, analysis tools, HDL glue
  • garnet Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+
  • magma - Meta HDL, 2017+
  • migen - Meta HDL, 2013+
  • MyHDL - Process based HDL, verification framework included, 2004+
  • PyRTL - Meta HDL, simulator suitable for research.
  • PyMTL - Process based HDL, verification framework included, 2014+
  • veriloggen - 2015-?, Python, Verilog centric meta HDL with HLS like features

• Ruby

  • RHDL

• Rust

  • hoodlum - Meta HDL, 2016+

• Scala

  • chisel - Meta HDL, 2012+
  • SpinalHDL - Meta HDL 2012+

HLS

• hlslibs - ac_math, ac_dsp, ac_types
• legup - 2011-2015, LLVM based c->verilog
• bambu - 2003-?, GCC based c->verilog
• augh - c->verilog, DSP support
• https://github.com/utwente-fmt - abstract hls, verification libraries
• Shang - 2012-2014, LLVM based, c->verilog
• xronos - 2012, java, simple HLS
• Potholes - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
• hls_recurse - 2015-2016 - conversion of recursive fn. for stackless architectures
• hg_lvl_syn - 2010, ILP, Force Directed scheduler
• abc <2008-?, A System for Sequential Synthesis and Verification
• polyphony - 2015-2017, simple python to hdl
• DelayGraph - 2016, C#, register assignment algorithms
• ahaHLS - 2019, An open source high level synthesis (HLS) tool using LLVM
• combinatorylogic/soc - 2019, An experimental System-on-Chip with a custom compiler toolchain.

Other HDL languages

• act - asynchronous circuit/compiler tools
• autopiper

Hardware Intermediate Representations

• coreir - 2016-?, LLVM HW compiler## License
• lgraph - 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design
• firrtl - 2016-?, Flexible Intermediate Representation for RTL

Synthesis tools

• vtr-verilog-to-routing
• yosys - RTL synthesis framework

Libraries with informations about boards/chips

• loam - Buildsystem for magma
• litex - Buildsystem for migen

Visualization and Documentation generators

• bitfield - Javascript bit field diagram renderer
• d3-wave - Javascript wave graph visualizer for RTL simulations
• d3-hwschematic - Javascript hierarchycal schematic visualizer for HDLs
• wavedrom - Javascript wave graph visualizer for documentations and sim.
• netlistsvg - Javascript schematic visualizer
• sphinx-hwt - Plugin for sphinx documentation generator which adds shematic into html documentaion.

HDL parsers

• hdlConvertor - Fast (System) Verilog/VHDL parser writen as C++ extension for Python
• pyVHDLParser - VHDL parser written in Python
• rust_hdl - VHDL parser and language server written in Rust

Other Simulation tools

• midas - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
• cocotb - A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Open Hardware

• opencores.org - webpage which hosts many openhardware projects
• ohwr - Open Hardware Repository, Cern open hardware community.
• enjoy-digital repositories - Migen, SoC level modules
• ZipCPU repositories - Verilog, mostly peripherals, DSP
• rhea - MyHDL, SoC level modules
• FPGAwars FPGA-peripherals - Verilog, simple peripherals
• PoC - VHDL, utils
• picorv32 - Verilog, A Size-Optimized RISC-V SoC
• openrisc - OpenRISC, FuseSoC, peripherals and cpu parts
• NyuziProcessor - GPGPU
• Miaow - Miaow, Southern Island compatible ISA compute only GPGPU
• VexRiscv - RISC-V written in SpinalHDL
• Awesome Open Hardware Verification - A list of open source tools and frameworks for hardware verification.

License

To the extent possible under law, Aliaksei Chapyzhenka has waived all copyright and related or neighboring rights to this work.