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[AArch64InstPrinter] Change printAddSubImm to comment imm value when … #3153

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Aug 10, 2021
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[AArch64InstPrinter] Change printAddSubImm to comment imm value when … #3153

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8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
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Expand Up @@ -962,11 +962,11 @@ void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
unsigned Shift =
AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
O << '#' << formatImm(Val);
if (Shift != 0)
if (Shift != 0) {
printShifter(MI, OpNum + 1, STI, O);

if (CommentStream)
*CommentStream << '=' << formatImm(Val << Shift) << '\n';
if (CommentStream)
*CommentStream << '=' << formatImm(Val << Shift) << '\n';
}
} else {
assert(MO.isExpr() && "Unexpected operand type!");
MO.getExpr()->print(O, &MAI);
Expand Down
33 changes: 16 additions & 17 deletions llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
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Expand Up @@ -325,7 +325,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
;
; CHECK-NOLSE-O0-LABEL: fetch_and_nand:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
Expand Down Expand Up @@ -355,7 +355,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB6_1
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: fetch_and_nand:
Expand All @@ -373,7 +373,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
;
; CHECK-LSE-O0-LABEL: fetch_and_nand:
; CHECK-LSE-O0: ; %bb.0:
; CHECK-LSE-O0-NEXT: sub sp, sp, #32 ; =32
; CHECK-LSE-O0-NEXT: sub sp, sp, #32
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: ldr w8, [x0]
; CHECK-LSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
Expand All @@ -392,7 +392,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB6_1
; CHECK-LSE-O0-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-LSE-O0-NEXT: add sp, sp, #32
; CHECK-LSE-O0-NEXT: ret
%val = atomicrmw nand i32* %p, i32 7 release
ret i32 %val
Expand All @@ -414,7 +414,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
;
; CHECK-NOLSE-O0-LABEL: fetch_and_nand_64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
Expand Down Expand Up @@ -444,7 +444,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB7_1
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: fetch_and_nand_64:
Expand All @@ -462,7 +462,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
;
; CHECK-LSE-O0-LABEL: fetch_and_nand_64:
; CHECK-LSE-O0: ; %bb.0:
; CHECK-LSE-O0-NEXT: sub sp, sp, #32 ; =32
; CHECK-LSE-O0-NEXT: sub sp, sp, #32
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: ldr x8, [x0]
; CHECK-LSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
Expand All @@ -481,7 +481,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB7_1
; CHECK-LSE-O0-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-LSE-O0-NEXT: add sp, sp, #32
; CHECK-LSE-O0-NEXT: ret
%val = atomicrmw nand i64* %p, i64 7 acq_rel
ret i64 %val
Expand All @@ -503,7 +503,7 @@ define i32 @fetch_and_or(i32* %p) #0 {
;
; CHECK-NOLSE-O0-LABEL: fetch_and_or:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
Expand Down Expand Up @@ -533,7 +533,7 @@ define i32 @fetch_and_or(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB8_1
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: fetch_and_or:
Expand Down Expand Up @@ -566,7 +566,7 @@ define i64 @fetch_and_or_64(i64* %p) #0 {
;
; CHECK-NOLSE-O0-LABEL: fetch_and_or_64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
Expand Down Expand Up @@ -595,7 +595,7 @@ define i64 @fetch_and_or_64(i64* %p) #0 {
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB9_1
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: fetch_and_or_64:
Expand Down Expand Up @@ -709,7 +709,7 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x8]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256 ; =256
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256
; CHECK-NOLSE-O0-NEXT: ldrb w9, [x9]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
Expand All @@ -735,7 +735,7 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw
; CHECK-LSE-O0-NEXT: ldrb w8, [x8]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-LSE-O0-NEXT: subs x9, x0, #256 ; =256
; CHECK-LSE-O0-NEXT: subs x9, x0, #256
; CHECK-LSE-O0-NEXT: ldrb w9, [x9]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb
; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
Expand Down Expand Up @@ -779,7 +779,7 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw #1
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x8]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256 ; =256
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256
; CHECK-NOLSE-O0-NEXT: ldrh w9, [x9]
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
Expand All @@ -805,7 +805,7 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw #1
; CHECK-LSE-O0-NEXT: ldrh w8, [x8]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-LSE-O0-NEXT: subs x9, x0, #256 ; =256
; CHECK-LSE-O0-NEXT: subs x9, x0, #256
; CHECK-LSE-O0-NEXT: ldrh w9, [x9]
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth
; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
Expand Down Expand Up @@ -1323,5 +1323,4 @@ define void @store_trunc(i32 %val, i8* %p8, i16* %p16) {
ret void
}


attributes #0 = { nounwind }
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
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Expand Up @@ -6,15 +6,15 @@ declare void @byval_i32(i32* byval(i32) %ptr)
define void @call_byval_i32(i32* %incoming) {
; CHECK-LABEL: call_byval_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32
; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: str w8, [sp]
; CHECK-NEXT: bl byval_i32
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32 // =32
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
call void @byval_i32(i32* byval(i32) %incoming)
ret void
Expand All @@ -25,10 +25,10 @@ declare void @byval_a64i32([64 x i32]* byval([64 x i32]) %ptr)
define void @call_byval_a64i32([64 x i32]* %incoming) {
; CHECK-LABEL: call_byval_a64i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #288 // =288
; CHECK-NEXT: sub sp, sp, #288
; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
; CHECK-NEXT: str x28, [sp, #272] // 8-byte Folded Spill
; CHECK-NEXT: add x29, sp, #256 // =256
; CHECK-NEXT: add x29, sp, #256
; CHECK-NEXT: .cfi_def_cfa w29, 32
; CHECK-NEXT: .cfi_offset w28, -16
; CHECK-NEXT: .cfi_offset w30, -24
Expand Down Expand Up @@ -68,7 +68,7 @@ define void @call_byval_a64i32([64 x i32]* %incoming) {
; CHECK-NEXT: bl byval_a64i32
; CHECK-NEXT: ldr x28, [sp, #272] // 8-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #288 // =288
; CHECK-NEXT: add sp, sp, #288
; CHECK-NEXT: ret
call void @byval_a64i32([64 x i32]* byval([64 x i32]) %incoming)
ret void
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
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Expand Up @@ -30,7 +30,7 @@ declare void @puts(i8*)
define i32 @test_musttail_variadic_spill(i32 %arg0, ...) {
; CHECK-LABEL: test_musttail_variadic_spill:
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #224 ; =224
; CHECK-NEXT: sub sp, sp, #224
; CHECK-NEXT: stp x28, x27, [sp, #128] ; 16-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #144] ; 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #160] ; 16-byte Folded Spill
Expand Down Expand Up @@ -87,7 +87,7 @@ define i32 @test_musttail_variadic_spill(i32 %arg0, ...) {
; CHECK-NEXT: ldp x24, x23, [sp, #160] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #144] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x28, x27, [sp, #128] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #224 ; =224
; CHECK-NEXT: add sp, sp, #224
; CHECK-NEXT: b _musttail_variadic_callee
; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
Expand All @@ -102,7 +102,7 @@ declare void(i8*, ...)* @get_f(i8* %this)
define void @f_thunk(i8* %this, ...) {
; CHECK-LABEL: f_thunk:
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #256 ; =256
; CHECK-NEXT: sub sp, sp, #256
; CHECK-NEXT: stp x28, x27, [sp, #160] ; 16-byte Folded Spill
; CHECK-NEXT: stp x26, x25, [sp, #176] ; 16-byte Folded Spill
; CHECK-NEXT: stp x24, x23, [sp, #192] ; 16-byte Folded Spill
Expand All @@ -123,8 +123,8 @@ define void @f_thunk(i8* %this, ...) {
; CHECK-NEXT: .cfi_offset w27, -88
; CHECK-NEXT: .cfi_offset w28, -96
; CHECK-NEXT: mov x27, x8
; CHECK-NEXT: add x8, sp, #128 ; =128
; CHECK-NEXT: add x9, sp, #256 ; =256
; CHECK-NEXT: add x8, sp, #128
; CHECK-NEXT: add x9, sp, #256
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: mov x20, x1
; CHECK-NEXT: mov x21, x2
Expand Down Expand Up @@ -159,7 +159,7 @@ define void @f_thunk(i8* %this, ...) {
; CHECK-NEXT: ldp x24, x23, [sp, #192] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #176] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x28, x27, [sp, #160] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #256 ; =256
; CHECK-NEXT: add sp, sp, #256
; CHECK-NEXT: br x9
%ap = alloca [4 x i8*], align 16
%ap_i8 = bitcast [4 x i8*]* %ap to i8*
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
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Expand Up @@ -67,12 +67,12 @@ define <2 x i32> @freeze_ivec() {
define i8* @freeze_ptr() {
; CHECK-LABEL: freeze_ptr:
; CHECK: // %bb.0:
; CHECK-NEXT: add x0, x8, #4 // =4
; CHECK-NEXT: add x0, x8, #4
; CHECK-NEXT: ret
;
; GISEL-LABEL: freeze_ptr:
; GISEL: // %bb.0:
; GISEL-NEXT: add x0, x8, #4 // =4
; GISEL-NEXT: add x0, x8, #4
; GISEL-NEXT: ret
%y1 = freeze i8* undef
%t1 = getelementptr i8, i8* %y1, i64 4
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
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Expand Up @@ -154,14 +154,14 @@ entry:
}
; CHECK-LABEL: novla_nodynamicrealign_nocall
; Check that space is reserved for one local variable on the stack.
; CHECK: sub sp, sp, #16 // =16
; CHECK: sub sp, sp, #16
; Check correct access to arguments passed on the stack, through stack pointer
; CHECK: ldr d[[DARG:[0-9]+]], [sp, #40]
; CHECK: ldr w[[IARG:[0-9]+]], [sp, #24]
; Check correct access to local variable on the stack, through stack pointer
; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12]
; Check epilogue:
; CHECK: add sp, sp, #16 // =16
; CHECK: add sp, sp, #16
; CHECK: ret


Expand Down Expand Up @@ -394,7 +394,7 @@ entry:
; bytes & the base pointer (x19) gets initialized to
; this 128-byte aligned area for local variables &
; spill slots
; CHECK: sub x9, sp, #80 // =80
; CHECK: sub x9, sp, #80
; CHECK: and sp, x9, #0xffffffffffffff80
; CHECK: mov x19, sp
; Check correctness of cfi pseudo-instructions
Expand Down Expand Up @@ -688,7 +688,7 @@ bb1:
; CHECK-LABEL: realign_conditional2
; Extra realignment in the prologue (performance issue).
; CHECK: tbz {{.*}} .[[LABEL:.*]]
; CHECK: sub x9, sp, #32 // =32
; CHECK: sub x9, sp, #32
; CHECK: and sp, x9, #0xffffffffffffffe0
; CHECK: mov x19, sp
; Stack is realigned in a non-entry BB.
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
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Expand Up @@ -23,15 +23,15 @@ define <2 x i16> @test1(<2 x i16>* %v2i16_ptr) {
; CHECK-LE-LABEL: test1:
; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: ld1 { v0.h }[0], [x0]
; CHECK-LE-NEXT: add x8, x0, #2 // =2
; CHECK-LE-NEXT: add x8, x0, #2
; CHECK-LE-NEXT: ld1 { v0.h }[2], [x8]
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test1:
; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ld1 { v0.h }[0], [x0]
; CHECK-BE-NEXT: add x8, x0, #2 // =2
; CHECK-BE-NEXT: add x8, x0, #2
; CHECK-BE-NEXT: ld1 { v0.h }[2], [x8]
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
; CHECK-BE-NEXT: ret
Expand Down Expand Up @@ -67,15 +67,15 @@ define <2 x i8> @test3(<2 x i8>* %v2i8_ptr) {
; CHECK-LE-LABEL: test3:
; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: ld1 { v0.b }[0], [x0]
; CHECK-LE-NEXT: add x8, x0, #1 // =1
; CHECK-LE-NEXT: add x8, x0, #1
; CHECK-LE-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test3:
; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ld1 { v0.b }[0], [x0]
; CHECK-BE-NEXT: add x8, x0, #1 // =1
; CHECK-BE-NEXT: add x8, x0, #1
; CHECK-BE-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
; CHECK-BE-NEXT: ret
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
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Expand Up @@ -13,8 +13,8 @@ define void @matrix_mul_unsigned(i32 %N, i32* nocapture %C, i16* nocapture reado
; CHECK-NEXT: add x9, x2, w0, uxtw #1
; CHECK-NEXT: ldp d1, d2, [x9]
; CHECK-NEXT: add x9, x1, w0, uxtw #2
; CHECK-NEXT: subs x8, x8, #8 // =8
; CHECK-NEXT: add w0, w0, #8 // =8
; CHECK-NEXT: subs x8, x8, #8
; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h
; CHECK-NEXT: stp q1, q2, [x9]
Expand Down Expand Up @@ -77,8 +77,8 @@ define void @matrix_mul_signed(i32 %N, i32* nocapture %C, i16* nocapture readonl
; CHECK-NEXT: add x9, x2, w0, sxtw #1
; CHECK-NEXT: ldp d1, d2, [x9]
; CHECK-NEXT: add x9, x1, w0, sxtw #2
; CHECK-NEXT: subs x8, x8, #8 // =8
; CHECK-NEXT: add w0, w0, #8 // =8
; CHECK-NEXT: subs x8, x8, #8
; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: smull v2.4s, v0.4h, v2.4h
; CHECK-NEXT: stp q1, q2, [x9]
Expand Down Expand Up @@ -141,11 +141,11 @@ define void @matrix_mul_double_shuffle(i32 %N, i32* nocapture %C, i16* nocapture
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh w9, [x2], #16
; CHECK-NEXT: mov w10, w0
; CHECK-NEXT: subs x8, x8, #8 // =8
; CHECK-NEXT: subs x8, x8, #8
; CHECK-NEXT: lsl x10, x10, #2
; CHECK-NEXT: dup v1.4h, w9
; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: add w0, w0, #8 // =8
; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: str q1, [x1, x10]
; CHECK-NEXT: b.ne .LBB2_1
; CHECK-NEXT: // %bb.2: // %for.end12
Expand Down
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