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taiki-e · Nov 9, 2024 · 16816f4 · 16816f4
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commit 16816f4
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Showing 8 changed files with 10 additions and 12 deletions.
diff --git a/src/imp/atomic128/aarch64.rs b/src/imp/atomic128/aarch64.rs
@@ -1103,7 +1103,7 @@ unsafe fn _atomic_store_stp(dst: *mut u128, val: u128, order: Ordering) {
                 _atomic_swap_swpp(dst, val, order);
             }
 
-            // if compile_time(FEAT_LRCPC3) && order != relaxed:
+            // if compile_time(FEAT_LRCPC3) && order != relaxed => stilp
             // SAFETY: cfg guarantee that the CPU supports FEAT_LRCPC3.
             #[cfg(any(target_feature = "rcpc3", portable_atomic_target_feature = "rcpc3"))]
             Ordering::Release => _atomic_store_stilp(dst, val, order),

diff --git a/src/imp/atomic128/powerpc64.rs b/src/imp/atomic128/powerpc64.rs
@@ -197,7 +197,7 @@ unsafe fn atomic_load_pwr8(src: *mut u128, order: Ordering) -> u128 {
 
     // SAFETY: the caller must uphold the safety contract.
     //
-    // Refs: "3.3.4 Fixed Point Load and Store Quadword Instructions" of Power ISA
+    // Refs: Section 3.3.4 "Fixed Point Load and Store Quadword Instructions" of Power ISA 3.1C Book I
     unsafe {
         let (out_hi, out_lo);
         macro_rules! atomic_load_acquire {
@@ -309,7 +309,7 @@ unsafe fn atomic_store_pwr8(dst: *mut u128, val: u128, order: Ordering) {
 
     // SAFETY: the caller must uphold the safety contract.
     //
-    // Refs: "3.3.4 Fixed Point Load and Store Quadword Instructions" of Power ISA
+    // Refs: Section 3.3.4 "Fixed Point Load and Store Quadword Instructions" of Power ISA 3.1C Book I
     unsafe {
         let val = U128 { whole: val };
         macro_rules! atomic_store {
@@ -378,7 +378,7 @@ unsafe fn atomic_compare_exchange_pwr8(
 
     // SAFETY: the caller must uphold the safety contract.
     //
-    // Refs: "4.6.2.2 128-bit Load And Reserve and Store Conditional Instructions" of Power ISA
+    // Refs: Section 4.6.2.2 "128-bit Load And Reserve and Store Conditional Instructions" of Power ISA 3.1C Book II
     unsafe {
         let old = U128 { whole: old };
         let new = U128 { whole: new };
@@ -468,7 +468,7 @@ unsafe fn atomic_compare_exchange_weak_pwr8(
 
     // SAFETY: the caller must uphold the safety contract.
     //
-    // Refs: "4.6.2.2 128-bit Load And Reserve and Store Conditional Instructions" of Power ISA
+    // Refs: Section 4.6.2.2 "128-bit Load And Reserve and Store Conditional Instructions" of Power ISA 3.1C Book II
     unsafe {
         let old = U128 { whole: old };
         let new = U128 { whole: new };

diff --git a/src/imp/atomic128/riscv64.rs b/src/imp/atomic128/riscv64.rs
@@ -8,7 +8,6 @@ this module and use intrinsics.rs instead.
 
 Refs:
 - RISC-V Instruction Set Manual
-  https://github.com/riscv/riscv-isa-manual/tree/riscv-isa-release-8b9dc50-2024-08-30
   "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
   https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-8b9dc50-2024-08-30/src/zacas.adoc
 - RISC-V Atomics ABI Specification

diff --git a/src/imp/atomic128/s390x.rs b/src/imp/atomic128/s390x.rs
@@ -19,7 +19,6 @@ this module and use intrinsics.rs instead.
 
 Refs:
 - z/Architecture Principles of Operation https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
-- z/Architecture Reference Summary https://www.ibm.com/support/pages/zarchitecture-reference-summary
 - atomic-maybe-uninit https://github.com/taiki-e/atomic-maybe-uninit
 
 Generated asm:

diff --git a/src/imp/atomic64/riscv32.rs b/src/imp/atomic64/riscv32.rs
@@ -8,7 +8,6 @@ this module and use fallback implementation instead.
 
 Refs:
 - RISC-V Instruction Set Manual
-  https://github.com/riscv/riscv-isa-manual/tree/riscv-isa-release-8b9dc50-2024-08-30
   "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
   https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-8b9dc50-2024-08-30/src/zacas.adoc
 - RISC-V Atomics ABI Specification

diff --git a/src/imp/detect/auxv.rs b/src/imp/detect/auxv.rs
@@ -12,7 +12,7 @@ Supported platforms:
   https://github.com/bminor/glibc/commit/c7683a6d02f3ed59f5cd119b3e8547f45a15912f
   Always available on:
   - aarch64 (glibc 2.17+ https://github.com/bminor/glibc/blob/glibc-2.17/NEWS#L36)
-  - powerpc64 (le) (glibc 2.19+ https://github.com/bminor/glibc/blob/glibc-2.19/NEWS#L108)
+  - powerpc64 (le) (glibc 2.19+ or RHEL/CentOS's patched glibc 2.17+ https://github.com/bminor/glibc/blob/glibc-2.19/NEWS#L108)
   Not always available on:
   - powerpc64 (be) (glibc 2.3+ https://github.com/bminor/glibc/blob/glibc-2.3/NEWS#L56)
   Since Rust 1.64, std requires glibc 2.17+ https://blog.rust-lang.org/2022/08/01/Increasing-glibc-kernel-requirements.html

diff --git a/src/imp/interrupt/xtensa.rs b/src/imp/interrupt/xtensa.rs
@@ -2,8 +2,10 @@
 
 /*
 Refs:
-- Xtensa Instruction Set Architecture (ISA) Reference Manual https://0x04.net/~mwk/doc/xtensa.pdf
-- Linux kernel's Xtensa atomic implementation https://github.com/torvalds/linux/blob/v6.11/arch/xtensa/include/asm/atomic.h
+- Xtensa Instruction Set Architecture (ISA) Summary for all Xtensa LX Processors
+  https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/silicon-solutions/compute-ip/isa-summary.pdf
+- Linux kernel's Xtensa atomic implementation
+  https://github.com/torvalds/linux/blob/v6.11/arch/xtensa/include/asm/atomic.h
 */
 
 use core::arch::asm;

diff --git a/src/imp/riscv.rs b/src/imp/riscv.rs
@@ -10,7 +10,6 @@ Also, optionally provides RMW implementation when force-amo or Zaamo target feat
 
 Refs:
 - RISC-V Instruction Set Manual
-  https://github.com/riscv/riscv-isa-manual/tree/riscv-isa-release-8b9dc50-2024-08-30
   "Zaamo" Extension for Atomic Memory Operations
   https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-8b9dc50-2024-08-30/src/a-st-ext.adoc#zaamo-extension-for-atomic-memory-operations
   "Zabha" Extension for Byte and Halfword Atomic Memory Operations