Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

ESP-IDF targets' Atomic*64 is not lock-free #122

Open
1 of 2 tasks
taiki-e opened this issue Sep 24, 2023 · 0 comments
Open
1 of 2 tasks

ESP-IDF targets' Atomic*64 is not lock-free #122

taiki-e opened this issue Sep 24, 2023 · 0 comments
Labels
O-riscv Target: RISC-V architecture O-xtensa Target: Xtensa processors

Comments

@taiki-e
Copy link
Owner

taiki-e commented Sep 24, 2023

As discussed in rust-lang/rust#115577, these are not lock-free, and I guess the standard library will eventually remove Atomic*64 on these targets.

  • First, currently Atomic*64::is_lock_free returns true on these targets, but it should not; fixed in 287ef3d
  • Second, while lock-based fallback will automatically be used when Atomic*64 is removed from the standard library, the atomic built-in implementation appears to be more efficient than lock-based fallback at least on single-core systems, so it would be preferable to adjust the fallback to use atomic builtins
@taiki-e taiki-e added O-riscv Target: RISC-V architecture O-xtensa Target: Xtensa processors labels Sep 24, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
O-riscv Target: RISC-V architecture O-xtensa Target: Xtensa processors
Projects
None yet
Development

No branches or pull requests

1 participant