Support dram memory space in metal direct #584
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
nsmithtt
requested review from
jnie-TT,
kmabeeTT,
AleksKnezevic,
sdjordjevicTT,
rpavlovicTT,
mrakitaTT,
nobradovictt and
tapspatel
as code owners
nsmithtt
force-pushed
the
nsmith/dram2
branch
2 times, most recently
from
7342259 to
c5ab0ca
Compare
rpavlovicTT
reviewed
Sep 4, 2024
lib/Dialect/TT/IR/TTOpsTypes.cpp
Outdated
Comment on lines
733
to
734
| mlir::ArrayRef<CoreCoordAttr> dramCores, unsigned dramChannelSize, | ||
| unsigned dramAddressAlignBytes, unsigned dramPageSize) { |
There was a problem hiding this comment.
dramChannelSize, dramAddressAlignBytes are unused params
rpavlovicTT
reviewed
Sep 4, 2024
lib/Dialect/TT/IR/TTOpsTypes.cpp
Outdated
| } | ||
|
|
||
| static mlir::AffineMap | ||
| createDramMap(::mlir::MLIRContext *context, GridAttr workerGrid, ArchAttr arch, |
There was a problem hiding this comment.
if you could just add comment for both functions createL1Map, createDramMap how map looks like for an example grid.
rpavlovicTT
approved these changes
Sep 4, 2024
This change adds support for the device dram memory space in metal backend. This required a few bits of refactoring including: - `DeviceAttr` splits out worker grid from L1 map, they now respectively map the physical compute cores and the physical L1 memory map. - `DeviceAttr` gets a new map, `dramMap`, which maps a linear tensor coordinate to a physical dram address. - Change `projectOnto` to take an arbitrary affine map instead of a grid attr. This let's us pass in unique affine map for L1 or DRAM or Eth (in the future) to the same interface. - `PhysicalCoreCoordMapping` can now take an L1 grid or a DRAM grid. - Giving explicit enum index names for the DeviceAttr affine map results. - Noc datamovement program can now be generated as reads or writes, necessary for writing to DRAM since dram cores do not have risc. Closes #359
nsmithtt
force-pushed
the
nsmith/dram2
branch
from
c5ab0ca to
fc498b9
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This change adds support for the device dram memory space in metal
backend. This required a few bits of refactoring including:
DeviceAttrsplits out worker grid from L1 map, they now respectivelymap the physical compute cores and the physical L1 memory map.
DeviceAttrgets a new map,dramMap, which maps a linear tensorcoordinate to a physical dram address.
projectOntoto take an arbitrary affine map instead of a gridattr. This let's us pass in unique affine map for L1 or DRAM or Eth
(in the future) to the same interface.
PhysicalCoreCoordMappingcan now take an L1 grid or a DRAM grid.results.
necessary for writing to DRAM since dram cores do not have risc.
Closes #359