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[aarch64] atan2 intrinsic lowering (p5)
This change is part of this proposal: https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294 - `VecFuncs.def`: define intrinsic to sleef/armpl mapping - `LegalizerHelper.cpp`: add missing fewerElementsVector handling for the new atan2 intrinsic - `AArch64ISelLowering.cpp`: Add arch64 specializations for lowering like neon instructions - `AArch64LegalizerInfo.cpp`: Legalize atan2. Part 5 for Implement the atan2 HLSL Function llvm#70096.
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llvm/test/CodeGen/AArch64/GlobalISel/legalize-atan2.mir
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,255 @@ | ||
| # RUN: llc -verify-machineinstrs -mtriple aarch64--- \ | ||
| # RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \ | ||
| # RUN: | FileCheck %s | ||
| ... | ||
| --- | ||
| name: test_v4f16.atan2 | ||
| alignment: 4 | ||
| tracksRegLiveness: true | ||
| registers: | ||
| - { id: 0, class: _ } | ||
| - { id: 1, class: _ } | ||
| body: | | ||
| bb.0: | ||
| liveins: $d0, $d1 | ||
| ; CHECK-LABEL: name: test_v4f16.atan2 | ||
| ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>) | ||
| ; CHECK: [[V5:%[0-9]+]]:_(s16), [[V6:%[0-9]+]]:_(s16), [[V7:%[0-9]+]]:_(s16), [[V8:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>) | ||
| ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16) | ||
| ; CHECK-DAG: [[V5_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V5]](s16) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32) | ||
| ; CHECK-NEXT: $s1 = COPY [[V5_S32]](s32) | ||
| ; CHECK-NEXT: BL &atan2f | ||
| ; CHECK-NEXT: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32) | ||
| ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16) | ||
| ; CHECK-DAG: [[V6_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V6]](s16) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32) | ||
| ; CHECK-NEXT: $s1 = COPY [[V6_S32]](s32) | ||
| ; CHECK-NEXT: BL &atan2f | ||
| ; CHECK-NEXT: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32) | ||
| ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16) | ||
| ; CHECK-DAG: [[V7_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V7]](s16) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32) | ||
| ; CHECK-NEXT: $s1 = COPY [[V7_S32]](s32) | ||
| ; CHECK-NEXT: BL &atan2f | ||
| ; CHECK-NEXT: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32) | ||
| ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16) | ||
| ; CHECK-DAG: [[V8_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V8]](s16) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32) | ||
| ; CHECK-NEXT: $s1 = COPY [[V8_S32]](s32) | ||
| ; CHECK-NEXT: BL &atan2f | ||
| ; CHECK-NEXT: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32) | ||
| ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16) | ||
| %0:_(<4 x s16>) = COPY $d0 | ||
| %1:_(<4 x s16>) = COPY $d1 | ||
| %2:_(<4 x s16>) = G_FATAN2 %0, %1 | ||
| $d0 = COPY %2(<4 x s16>) | ||
| RET_ReallyLR implicit $d0 | ||
| ... | ||
| --- | ||
| name: test_v8f16.atan2 | ||
| alignment: 4 | ||
| tracksRegLiveness: true | ||
| registers: | ||
| - { id: 0, class: _ } | ||
| - { id: 1, class: _ } | ||
| body: | | ||
| bb.0: | ||
| liveins: $q0, $q1 | ||
| ; CHECK-LABEL: name: test_v8f16.atan2 | ||
| ; This is big, so let's just check for the 8 calls to atan2f, the the | ||
| ; G_UNMERGE_VALUES, and the G_BUILD_VECTOR. The other instructions ought | ||
| ; to be covered by the other tests. | ||
| ; CHECK: G_UNMERGE_VALUES | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: G_BUILD_VECTOR | ||
| %0:_(<8 x s16>) = COPY $q0 | ||
| %1:_(<8 x s16>) = COPY $q1 | ||
| %2:_(<8 x s16>) = G_FATAN2 %0, %1 | ||
| $q0 = COPY %2(<8 x s16>) | ||
| RET_ReallyLR implicit $q0 | ||
| ... | ||
| --- | ||
| name: test_v2f32.atan2 | ||
| alignment: 4 | ||
| tracksRegLiveness: true | ||
| registers: | ||
| - { id: 0, class: _ } | ||
| - { id: 1, class: _ } | ||
| body: | | ||
| bb.0: | ||
| liveins: $d0, $d1 | ||
| ; CHECK-LABEL: name: test_v2f32.atan2 | ||
| ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>) | ||
| ; CHECK: [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $s0 = COPY [[V1]](s32) | ||
| ; CHECK-DAG: $s1 = COPY [[V3]](s32) | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $s0 = COPY [[V2]](s32) | ||
| ; CHECK-DAG: $s1 = COPY [[V4]](s32) | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK: %2:_(<2 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32) | ||
| %0:_(<2 x s32>) = COPY $d0 | ||
| %1:_(<2 x s32>) = COPY $d1 | ||
| %2:_(<2 x s32>) = G_FATAN2 %0, %1 | ||
| $d0 = COPY %2(<2 x s32>) | ||
| RET_ReallyLR implicit $d0 | ||
| ... | ||
| --- | ||
| name: test_v4f32.atan2 | ||
| alignment: 4 | ||
| tracksRegLiveness: true | ||
| registers: | ||
| - { id: 0, class: _ } | ||
| - { id: 1, class: _ } | ||
| body: | | ||
| bb.0: | ||
| liveins: $q0, $q1 | ||
| ; CHECK-LABEL: name: test_v4f32.atan2 | ||
| ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32), [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>) | ||
| ; CHECK: [[V5:%[0-9]+]]:_(s32), [[V6:%[0-9]+]]:_(s32), [[V7:%[0-9]+]]:_(s32), [[V8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $s0 = COPY [[V1]](s32) | ||
| ; CHECK-DAG: $s1 = COPY [[V5]](s32) | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $s0 = COPY [[V2]](s32) | ||
| ; CHECK-DAG: $s1 = COPY [[V6]](s32) | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $s0 = COPY [[V3]](s32) | ||
| ; CHECK-DAG: $s1 = COPY [[V7]](s32) | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $s0 = COPY [[V4]](s32) | ||
| ; CHECK-DAG: $s1 = COPY [[V8]](s32) | ||
| ; CHECK: BL &atan2f | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK: %2:_(<4 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32), [[ELT3]](s32), [[ELT4]](s32) | ||
| %0:_(<4 x s32>) = COPY $q0 | ||
| %1:_(<4 x s32>) = COPY $q1 | ||
| %2:_(<4 x s32>) = G_FATAN2 %0, %1 | ||
| $q0 = COPY %2(<4 x s32>) | ||
| RET_ReallyLR implicit $q0 | ||
| ... | ||
| --- | ||
| name: test_v2f64.atan2 | ||
| alignment: 4 | ||
| tracksRegLiveness: true | ||
| registers: | ||
| - { id: 0, class: _ } | ||
| - { id: 1, class: _ } | ||
| body: | | ||
| bb.0: | ||
| liveins: $q0, $q1 | ||
| ; CHECK-LABEL: name: test_v2f64.atan2 | ||
| ; CHECK: [[V1:%[0-9]+]]:_(s64), [[V2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>) | ||
| ; CHECK: [[V3:%[0-9]+]]:_(s64), [[V4:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $d0 = COPY [[V1]](s64) | ||
| ; CHECK-DAG: $d1 = COPY [[V3]](s64) | ||
| ; CHECK: BL &atan2 | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s64) = COPY $d0 | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-DAG: $d0 = COPY [[V2]](s64) | ||
| ; CHECK-DAG: $d1 = COPY [[V4]](s64) | ||
| ; CHECK: BL &atan2 | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s64) = COPY $d0 | ||
| ; CHECK: %2:_(<2 x s64>) = G_BUILD_VECTOR [[ELT1]](s64), [[ELT2]](s64) | ||
| %0:_(<2 x s64>) = COPY $q0 | ||
| %1:_(<2 x s64>) = COPY $q1 | ||
| %2:_(<2 x s64>) = G_FATAN2 %0, %1 | ||
| $q0 = COPY %2(<2 x s64>) | ||
| RET_ReallyLR implicit $q0 | ||
| ... | ||
| --- | ||
| name: test_atan2_half | ||
| alignment: 4 | ||
| tracksRegLiveness: true | ||
| registers: | ||
| - { id: 0, class: _ } | ||
| - { id: 1, class: _ } | ||
| body: | | ||
| bb.0: | ||
| liveins: $h0, $h1 | ||
| ; CHECK-LABEL: name: test_atan2_half | ||
| ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16) | ||
| ; CHECK: [[REG2:%[0-9]+]]:_(s32) = G_FPEXT %1(s16) | ||
| ; CHECK-NEXT: ADJCALLSTACKDOWN | ||
| ; CHECK-NEXT: $s0 = COPY [[REG1]](s32) | ||
| ; CHECK-NEXT: $s1 = COPY [[REG2]](s32) | ||
| ; CHECK-NEXT: BL &atan2f | ||
| ; CHECK: ADJCALLSTACKUP | ||
| ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0 | ||
| ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32) | ||
| %0:_(s16) = COPY $h0 | ||
| %1:_(s16) = COPY $h1 | ||
| %2:_(s16) = G_FATAN2 %0, %1 | ||
| $h0 = COPY %2(s16) | ||
| RET_ReallyLR implicit $h0 |
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