Update golden testfiles for new write acknowledge

testfiles/bug-cernbe/repro.sv

@@ -28,7 +28,7 @@ module example
   reg wr_ack_int;
   reg [31:0] regA_reg;
   reg [1:0] regA_wreq;
-  reg [1:0] regA_wack;
+  wire [1:0] regA_wack;
   reg rd_ack_d0;
   reg [15:0] rd_dat_d0;
   reg wr_req_d0;
@@ -63,20 +63,17 @@ module example
 
   // Register regA
   assign regA_o = regA_reg;
+  assign regA_wack = regA_wreq;
   always_ff @(posedge(Clk))
   begin
     if (!rst_n)
-      begin
-        regA_reg <= 32'b00000000000000000000000000000000;
-        regA_wack <= 2'b0;
-      end
+      regA_reg <= 32'b00000000000000000000000000000000;
     else
       begin
         if (regA_wreq[0] == 1'b1)
           regA_reg[15:0] <= wr_dat_d0;
         if (regA_wreq[1] == 1'b1)
           regA_reg[31:16] <= wr_dat_d0;
-        regA_wack <= regA_wreq;
       end
   end
 

testfiles/bug-cernbe/repro.v

@@ -28,7 +28,7 @@ module example
   reg wr_ack_int;
   reg [31:0] regA_reg;
   reg [1:0] regA_wreq;
-  reg [1:0] regA_wack;
+  wire [1:0] regA_wack;
   reg rd_ack_d0;
   reg [15:0] rd_dat_d0;
   reg wr_req_d0;
@@ -63,20 +63,17 @@ module example
 
   // Register regA
   assign regA_o = regA_reg;
+  assign regA_wack = regA_wreq;
   always @(posedge(Clk))
   begin
     if (!rst_n)
-      begin
-        regA_reg <= 32'b00000000000000000000000000000000;
-        regA_wack <= 2'b0;
-      end
+      regA_reg <= 32'b00000000000000000000000000000000;
     else
       begin
         if (regA_wreq[0] == 1'b1)
           regA_reg[15:0] <= wr_dat_d0;
         if (regA_wreq[1] == 1'b1)
           regA_reg[31:16] <= wr_dat_d0;
-        regA_wack <= regA_wreq;
       end
   end
 

testfiles/bug-cernbe/repro.vhdl

@@ -68,19 +68,18 @@ begin
 
   -- Register regA
   regA_o <= regA_reg;
+  regA_wack <= regA_wreq;
   process (Clk) begin
     if rising_edge(Clk) then
       if rst_n = '0' then
         regA_reg <= "00000000000000000000000000000000";
-        regA_wack <= (others => '0');
       else
         if regA_wreq(0) = '1' then
           regA_reg(15 downto 0) <= wr_dat_d0;
         end if;
         if regA_wreq(1) = '1' then
           regA_reg(31 downto 16) <= wr_dat_d0;
         end if;
-        regA_wack <= regA_wreq;
       end if;
     end if;
   end process;

testfiles/bug-cernbe/sub_repro.sv

@@ -22,7 +22,7 @@ module sub_repro
   reg wr_ack_int;
   reg [15:0] subrA_reg;
   reg subrA_wreq;
-  reg subrA_wack;
+  wire subrA_wack;
   reg rd_ack_d0;
   reg [15:0] rd_dat_d0;
   reg wr_req_d0;
@@ -55,19 +55,14 @@ module sub_repro
 
   // Register subrA
   assign subrA_o = subrA_reg;
+  assign subrA_wack = subrA_wreq;
   always_ff @(posedge(Clk))
   begin
     if (!rst_n)
-      begin
-        subrA_reg <= 16'b0000000000000000;
-        subrA_wack <= 1'b0;
-      end
+      subrA_reg <= 16'b0000000000000000;
     else
-      begin
-        if (subrA_wreq == 1'b1)
-          subrA_reg <= wr_dat_d0;
-        subrA_wack <= subrA_wreq;
-      end
+      if (subrA_wreq == 1'b1)
+        subrA_reg <= wr_dat_d0;
   end
 
   // Register subrB

testfiles/bug-cernbe/sub_repro.v

@@ -22,7 +22,7 @@ module sub_repro
   reg wr_ack_int;
   reg [15:0] subrA_reg;
   reg subrA_wreq;
-  reg subrA_wack;
+  wire subrA_wack;
   reg rd_ack_d0;
   reg [15:0] rd_dat_d0;
   reg wr_req_d0;
@@ -55,19 +55,14 @@ module sub_repro
 
   // Register subrA
   assign subrA_o = subrA_reg;
+  assign subrA_wack = subrA_wreq;
   always @(posedge(Clk))
   begin
     if (!rst_n)
-      begin
-        subrA_reg <= 16'b0000000000000000;
-        subrA_wack <= 1'b0;
-      end
+      subrA_reg <= 16'b0000000000000000;
     else
-      begin
-        if (subrA_wreq == 1'b1)
-          subrA_reg <= wr_dat_d0;
-        subrA_wack <= subrA_wreq;
-      end
+      if (subrA_wreq == 1'b1)
+        subrA_reg <= wr_dat_d0;
   end
 
   // Register subrB

testfiles/bug-cernbe/sub_repro.vhdl

@@ -60,16 +60,15 @@ begin
 
   -- Register subrA
   subrA_o <= subrA_reg;
+  subrA_wack <= subrA_wreq;
   process (Clk) begin
     if rising_edge(Clk) then
       if rst_n = '0' then
         subrA_reg <= "0000000000000000";
-        subrA_wack <= '0';
       else
         if subrA_wreq = '1' then
           subrA_reg <= wr_dat_d0;
         end if;
-        subrA_wack <= subrA_wreq;
       end if;
     end if;
   end process;

testfiles/bug-empty/noinp.sv

@@ -40,10 +40,10 @@ module noinp
   reg wb_wip;
   reg [31:0] reg0_reg;
   reg reg0_wreq;
-  reg reg0_wack;
+  wire reg0_wack;
   reg [31:0] reg1_reg;
   reg reg1_wreq;
-  reg reg1_wack;
+  wire reg1_wack;
   reg rd_ack_d0;
   reg [31:0] rd_dat_d0;
   reg wr_req_d0;
@@ -102,36 +102,26 @@ module noinp
 
   // Register reg0
   assign noinp_inter.reg0 = reg0_reg;
+  assign reg0_wack = reg0_wreq;
   always_ff @(posedge(clk_i))
   begin
     if (!rst_n_i)
-      begin
-        reg0_reg <= 32'b00000000000000000000000000000000;
-        reg0_wack <= 1'b0;
-      end
+      reg0_reg <= 32'b00000000000000000000000000000000;
     else
-      begin
-        if (reg0_wreq == 1'b1)
-          reg0_reg <= wr_dat_d0;
-        reg0_wack <= reg0_wreq;
-      end
+      if (reg0_wreq == 1'b1)
+        reg0_reg <= wr_dat_d0;
   end
 
   // Register reg1
   assign noinp_inter.reg1 = reg1_reg;
+  assign reg1_wack = reg1_wreq;
   always_ff @(posedge(clk_i))
   begin
     if (!rst_n_i)
-      begin
-        reg1_reg <= 32'b00000000000000000000000100100011;
-        reg1_wack <= 1'b0;
-      end
+      reg1_reg <= 32'b00000000000000000000000100100011;
     else
-      begin
-        if (reg1_wreq == 1'b1)
-          reg1_reg <= wr_dat_d0;
-        reg1_wack <= reg1_wreq;
-      end
+      if (reg1_wreq == 1'b1)
+        reg1_reg <= wr_dat_d0;
   end
 
   // Process for write requests.

testfiles/bug-empty/noinp.v

@@ -40,10 +40,10 @@ module noinp
   reg wb_wip;
   reg [31:0] reg0_reg;
   reg reg0_wreq;
-  reg reg0_wack;
+  wire reg0_wack;
   reg [31:0] reg1_reg;
   reg reg1_wreq;
-  reg reg1_wack;
+  wire reg1_wack;
   reg rd_ack_d0;
   reg [31:0] rd_dat_d0;
   reg wr_req_d0;
@@ -102,36 +102,26 @@ module noinp
 
   // Register reg0
   assign noinp_inter.reg0 = reg0_reg;
+  assign reg0_wack = reg0_wreq;
   always @(posedge(clk_i))
   begin
     if (!rst_n_i)
-      begin
-        reg0_reg <= 32'b00000000000000000000000000000000;
-        reg0_wack <= 1'b0;
-      end
+      reg0_reg <= 32'b00000000000000000000000000000000;
     else
-      begin
-        if (reg0_wreq == 1'b1)
-          reg0_reg <= wr_dat_d0;
-        reg0_wack <= reg0_wreq;
-      end
+      if (reg0_wreq == 1'b1)
+        reg0_reg <= wr_dat_d0;
   end
 
   // Register reg1
   assign noinp_inter.reg1 = reg1_reg;
+  assign reg1_wack = reg1_wreq;
   always @(posedge(clk_i))
   begin
     if (!rst_n_i)
-      begin
-        reg1_reg <= 32'b00000000000000000000000100100011;
-        reg1_wack <= 1'b0;
-      end
+      reg1_reg <= 32'b00000000000000000000000100100011;
     else
-      begin
-        if (reg1_wreq == 1'b1)
-          reg1_reg <= wr_dat_d0;
-        reg1_wack <= reg1_wreq;
-      end
+      if (reg1_wreq == 1'b1)
+        reg1_reg <= wr_dat_d0;
   end
 
   // Process for write requests.

testfiles/bug-empty/noinp.vhdl

@@ -110,32 +110,30 @@ begin
 
   -- Register reg0
   noinp_inter_o.reg0 <= reg0_reg;
+  reg0_wack <= reg0_wreq;
   process (clk_i) begin
     if rising_edge(clk_i) then
       if rst_n_i = '0' then
         reg0_reg <= "00000000000000000000000000000000";
-        reg0_wack <= '0';
       else
         if reg0_wreq = '1' then
           reg0_reg <= wr_dat_d0;
         end if;
-        reg0_wack <= reg0_wreq;
       end if;
     end if;
   end process;
 
   -- Register reg1
   noinp_inter_o.reg1 <= reg1_reg;
+  reg1_wack <= reg1_wreq;
   process (clk_i) begin
     if rising_edge(clk_i) then
       if rst_n_i = '0' then
         reg1_reg <= "00000000000000000000000100100011";
-        reg1_wack <= '0';
       else
         if reg1_wreq = '1' then
           reg1_reg <= wr_dat_d0;
         end if;
-        reg1_wack <= reg1_wreq;
       end if;
     end if;
   end process;

testfiles/bug-gen_wt/m1.sv

@@ -27,7 +27,7 @@ module m1
   reg wr_ack_int;
   reg [31:0] r1_reg;
   reg r1_wreq;
-  reg r1_wack;
+  wire r1_wack;
   reg rd_ack_d0;
   reg [31:0] rd_dat_d0;
   reg wr_req_d0;
@@ -61,19 +61,14 @@ module m1
 
   // Register r1
   assign r1_o = r1_reg;
+  assign r1_wack = r1_wreq;
   always_ff @(posedge(Clk))
   begin
     if (!rst_n)
-      begin
-        r1_reg <= 32'b00000000000000000000000000000000;
-        r1_wack <= 1'b0;
-      end
+      r1_reg <= 32'b00000000000000000000000000000000;
     else
-      begin
-        if (r1_wreq == 1'b1)
-          r1_reg <= wr_dat_d0;
-        r1_wack <= r1_wreq;
-      end
+      if (r1_wreq == 1'b1)
+        r1_reg <= wr_dat_d0;
   end
 
   // Interface sm2

testfiles/bug-gen_wt/m1.v

@@ -27,7 +27,7 @@ module m1
   reg wr_ack_int;
   reg [31:0] r1_reg;
   reg r1_wreq;
-  reg r1_wack;
+  wire r1_wack;
   reg rd_ack_d0;
   reg [31:0] rd_dat_d0;
   reg wr_req_d0;
@@ -61,19 +61,14 @@ module m1
 
   // Register r1
   assign r1_o = r1_reg;
+  assign r1_wack = r1_wreq;
   always @(posedge(Clk))
   begin
     if (!rst_n)
-      begin
-        r1_reg <= 32'b00000000000000000000000000000000;
-        r1_wack <= 1'b0;
-      end
+      r1_reg <= 32'b00000000000000000000000000000000;
     else
-      begin
-        if (r1_wreq == 1'b1)
-          r1_reg <= wr_dat_d0;
-        r1_wack <= r1_wreq;
-      end
+      if (r1_wreq == 1'b1)
+        r1_reg <= wr_dat_d0;
   end
 
   // Interface sm2