arch: fw: mpp scheduling using zephyr

SOF MPP scheduling description and flows using
zephyr rtos infrastructure

Signed-off-by: Michal Wasko <michal.wasko@intel.com>

architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/edf_scheduling.diag

@@ -0,0 +1,39 @@
+blockdiag edf_scheduling {
+
+	node_width = 250;
+	node_height = 120;
+	default_fontsize = 16;
+
+	Comp_1 -> Comp_2
+	comment_1 -> Comp_2 [style=dashed]
+	Comp_2 -> Comp_3
+	comment_2 -> Comp_3 [style=dashed]
+	Comp_3 -> Comp_4
+	comment_3 -> Comp_4 [style=dashed]
+	Comp_4 -> sink
+	comment_4 -> sink [style=dashed]
+
+	Comp_1 [label="DP component 1\n
+		*processing period\n
+		*compute requirement"]
+	Comp_2 [label="DP component 2\n
+		*processing period\n
+		*compute requirement"]
+	Comp_3 [label="DP component 3\n
+		*processing period\n
+		*compute requirement"]
+	Comp_4 [label="DP component 4\n
+		*processing period\n
+		*compute requirement"]
+
+	sink [label="real time sink", shape=endpoint, fontsize = 16]
+
+	comment_1 [label="DP1 to deliver data let\n
+		DP2 meet its objective"]
+	comment_2 [label="DP2 to deliver data let\n
+		DP3 meet its objective"]
+	comment_3 [label="DP3 to deliver data let\n
+		DP4 meet its objective"]
+	comment_4 [label="DP4 to deliver data\n
+		to real time-sink"]
+}

architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/example_DP_secondary_core_timeline.pu

@@ -0,0 +1,136 @@
+@startuml
+
+Title DP tasks scheduling on secondary DSP core
+
+legend
+Assumptions:
+1) 1ms scheduling
+2) No LL tasks assigned to example secondary DSP core
+3) DP Task B do not depend on Task A completion
+(otherwise, Task B would start on next timer interrupt after A
+completion)
+end legend
+
+scale 1 as 150 pixels
+
+concise "Task B" as Task_B
+concise "Task A" as Task_A
+
+concise "DP task processing" as DP_Processing
+robust "DSP" as DSP
+concise "Timer interrupt" as Interrupt
+
+
+@Task_A
+0 is Busy
+1.5 is {-}
+
+4 is Busy
+5.5 is {-}
+
+8 is Busy
+9.5 is {-}
+
+@0 <-> @4: Task A schedule period (4ms)
+@4 <-> @5.5: Task A execution time (1.5ms)
+
+DP_Processing@0 -[#Orange]> Task_A@0
+DP_Processing@1 -[#Orange]> Task_A@1
+DP_Processing@1.5 -[#Orange]> Task_A@1.5
+
+
+@Task_B
+0 is Busy
+2 is {-}
+
+6 is Busy
+8 is {-}
+
+@0 <-> @6: Task B schedule period (6ms)
+@6 <-> @8: Task B execution time (2ms)
+
+DP_Processing@1.5 -[#Brown]> Task_B@0
+DP_Processing@2 -[#Brown]> Task_B@0.5
+DP_Processing@3 -[#Brown]> Task_B@1.5
+DP_Processing@3.5 -[#Brown]> Task_B@2
+
+DSP is Idle
+DP_Processing is {-}
+
+@0
+DP_Processing is "A"
+
+@0
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DSP is "Scheduling"
+DP_Processing is "A"
+
+@1
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DP_Processing is "A"
+
+@1.5
+DP_Processing -> DSP
+DSP -> DP_Processing
+DP_Processing is "B"
+
+@2
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DP_Processing is "B"
+
+@3
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DP_Processing is "B"
+
+@3.5
+DP_Processing -> DSP
+DSP is Idle
+DP_Processing is {-}
+
+@4
+Interrupt -[#DarkViolet]> DSP
+DSP is "Scheduling"
+DSP -> DP_Processing
+DP_Processing is "A"
+
+@5
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DP_Processing is "A"
+
+@5.5
+DP_Processing -> DSP
+DSP is Idle
+DP_Processing is {-}
+
+@6.001
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DSP is "Scheduling"
+DP_Processing is "B"
+
+@7.001
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DP_Processing is "B"
+
+@8.001
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DP_Processing is "A"
+
+@9.001
+Interrupt -[#DarkViolet]> DSP
+DSP -> DP_Processing
+DP_Processing is "A"
+
+@9.5
+DP_Processing -> DSP
+DSP is Idle
+DP_Processing is {-}
+
+@enduml

architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/example_LL_DP_timeline.pu

@@ -0,0 +1,95 @@
+@startuml
+
+Title Task scheduling on DSP core
+
+legend
+Assumptions:
+1) 1ms scheduling
+2) 0.1ms takes LL task execution
+3) 0.5ms takes execution of all DP tasks
+end legend
+
+scale 1 as 200 pixels
+
+concise "DP Tasks Processing" as DP_Processing
+concise "LL Tasks Processing" as LL_Processing
+robust "DSP" as DSP
+concise "Timer Interrupt" as Interrupt
+
+DSP is Idle
+
+@DSP
+@1.2 <-> @2: Time available for\nDP tasks execution
+@2.2 <-> @2.7: Actual execution time\nof DP tasks
+@3 <-> @3.2: Actual execution time\nof LL tasks
+
+@Interrupt
+@0 <-> @1 : Schedule period
+
+@0
+Interrupt -> DSP
+DSP -> LL_Processing
+DSP is "Scheduling tasks"
+LL_Processing is Busy
+DP_Processing is {-}
+
+@+0.2
+DSP -> DP_Processing
+LL_Processing is {-}
+DP_Processing is Busy
+
+@+0.5
+DP_Processing -> DSP
+DP_Processing is {-}
+DSP is Idle
+
+@1
+Interrupt -> DSP
+DSP -> LL_Processing
+DSP is "Scheduling tasks"
+LL_Processing is Busy
+
+@+0.2
+DSP -> DP_Processing
+LL_Processing is {-}
+DP_Processing is Busy
+
+@+0.5
+DP_Processing -> DSP
+DP_Processing is {-}
+DSP is Idle
+
+@2
+Interrupt -> DSP
+DSP -> LL_Processing
+DSP is "Scheduling tasks"
+LL_Processing is Busy
+
+@+0.2
+DSP -> DP_Processing
+LL_Processing is {-}
+DP_Processing is Busy
+
+@+0.5
+DP_Processing -> DSP
+DP_Processing is {-}
+DSP is Idle
+
+@3
+Interrupt -> DSP
+DSP -> LL_Processing
+DSP is "Scheduling tasks"
+LL_Processing is Busy
+
+@+0.2
+DSP -> DP_Processing
+
+LL_Processing is {-}
+DP_Processing is Busy
+
+@+0.5
+DP_Processing -> DSP
+DP_Processing is {-}
+DSP is Idle
+
+@enduml

architectures/firmware/sof-zephyr/mpp_layer/images/mpp_scheduling/example_multiple_cores_timeline.pu

@@ -0,0 +1,108 @@
+@startuml
+
+Title Tasks scheduling on multiple DSP cores
+
+legend
+Assumptions:
+1) 1ms system tick
+
+Notes:
+2) Core #0 has only LL tasks assigned schedule in 1ms period
+3) Core #1 has one DP task assigned that is dependent on Core #0 LL tasks data, scheduled in 1ms period
+(e.g. multicore pipeline with DP module scheduled on separate core)
+4) Core #2 has LL tasks scheduled in 1ms period and DP task scheduled in 2ms period
+(e.g. pipeline processing with LL and DP components components where DP component has 2ms scheduling period)
+end legend
+
+scale 1 as 300 pixels
+
+concise "DSP #2" as DSP_2
+concise "DSP #1" as DSP_1
+concise "DSP #0" as DSP_0
+
+concise "Timer interrupt" as Interrupt
+
+@DSP_0
+0 is "LL proc."
+0.5 is {-}
+
+1 is "LL proc."
+1.5 is {-}
+
+2 is "LL proc."
+2.5 is {-}
+
+3 is "LL proc."
+3.5 is {-}
+
+4 is "LL proc."
+4.5 is {-}
+
+@0 <-> @1: DSP#0 LL schedule period (1ms)
+
+@DSP_1
+0 is {-}
+
+1 is "DP proc."
+1.6 is {-}
+
+2 is "DP proc."
+2.6 is {-}
+
+3 is "DP proc."
+3.6 is {-}
+
+4 is "DP proc."
+4.6 is {-}
+5 is {-}
+
+@0 <-> @1: delay one period (waiting for first DSP#0 LL data)
+@1 <-> @2: DSP#1 DP schedule period (1ms)
+
+@DSP_2
+
+0 is "LL proc."
+0.3 is {-}
+
+1 is "LL proc."
+1.3 is {-}
+
+2 is "LL proc."
+2.3 is "DP proc."
+
+3 is "LL proc."
+3.3 is "DP proc."
+3.7 is {-}
+
+4 is "LL proc."
+4.3 is "DP proc."
+
+@0 <-> @1: DSP#2 LL schedule period (1ms)
+@2.3 <-> @4.3: DSP#2 DP schedule period (2ms)
+
+@0
+Interrupt -[#DarkViolet]> DSP_0
+Interrupt -[#DarkViolet]> DSP_1
+Interrupt -[#DarkViolet]> DSP_2
+
+@1
+Interrupt -[#DarkViolet]> DSP_0
+Interrupt -[#DarkViolet]> DSP_1
+Interrupt -[#DarkViolet]> DSP_2
+
+@2
+Interrupt -[#DarkViolet]> DSP_0
+Interrupt -[#DarkViolet]> DSP_1
+Interrupt -[#DarkViolet]> DSP_2
+
+@3
+Interrupt -[#DarkViolet]> DSP_0
+Interrupt -[#DarkViolet]> DSP_1
+Interrupt -[#DarkViolet]> DSP_2
+
+@4
+Interrupt -[#DarkViolet]> DSP_0
+Interrupt -[#DarkViolet]> DSP_1
+Interrupt -[#DarkViolet]> DSP_2
+
+@enduml