intel_adsp: mtl: extra step for hst domain

This step for an HST power domain is only required on the ACE 1.5 generation platform. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
thesofproject · Dec 13, 2023 · 21cded2 · 21cded2
1 parent 7495eb0
commit 21cded2
Show file tree

Hide file tree

Showing 3 changed files with 27 additions and 0 deletions.
diff --git a/drivers/power_domain/power_domain_intel_adsp.c b/drivers/power_domain/power_domain_intel_adsp.c
@@ -9,6 +9,10 @@
 #include <zephyr/pm/device_runtime.h>
 #include <adsp_shim.h>
 
+#if CONFIG_ACE_VERSION_1_5
+#include <adsp_power.h>
+#endif /* CONFIG_ACE_VERSION_1_5 */
+
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF);
 
@@ -31,6 +35,16 @@ static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enabl
 			return -1;
 		}
 	} else {
+#if CONFIG_ACE_VERSION_1_5
+		extern uint32_t g_key_read_holder;
+
+		if (bits->SPA_bit == INTEL_ADSP_HST_DOMAIN_BIT) {
+			volatile uint32_t* key_read_ptr = SRAM_TO_SRAM_ALIAS(&g_key_read_holder);
+			uint32_t key_value = *key_read_ptr;
+			if (key_value != INTEL_ADSP_ACE15_MAGIC_KEY)
+				return -1;
+		}
+#endif
 		sys_write16(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrctl) & ~(SPA_bit_mask),
 			    (mem_addr_t)&ACE_DfPMCCU.dfpwrctl);
 	}

diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h b/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
@@ -98,4 +98,10 @@ static ALWAYS_INLINE bool soc_cpu_is_powered(int cpu_num)
  */
 #define INTEL_ADSP_HST_DOMAIN_DEV DEVICE_DT_GET(INTEL_ADSP_HST_DOMAIN_DTNODE)
 
+#define INTEL_ADSP_HST_DOMAIN_BIT DT_PROP(INTEL_ADSP_HST_DOMAIN_DTNODE, bit_position)
+
+#define INTEL_ADSP_ACE15_MAGIC_KEY 0xFFFACE15
+
+#define SRAM_TO_SRAM_ALIAS(address) ((__typeof__(address))((((uint32_t)(address)) & 0x1FFFFFFF) | 0x40000000))
+
 #endif /* ZEPHYR_SOC_INTEL_ADSP_POWER_H_ */
diff --git a/soc/xtensa/intel_adsp/ace/multiprocessing.c b/soc/xtensa/intel_adsp/ace/multiprocessing.c
@@ -26,6 +26,11 @@
 
 #define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc))
 
+#if CONFIG_ACE_VERSION_1_5
+__attribute__((__aligned__(CONFIG_DCACHE_LINE_SIZE))) uint32_t g_key_read_holder;
+__attribute__((__aligned__(CONFIG_DCACHE_LINE_SIZE))) unsigned alignment_dummy[0];
+#endif /* CONFIG_ACE_VERSION_1_5 */
+
 static void ipc_isr(void *arg)
 {
 	uint32_t cpu_id = arch_proc_id();
@@ -86,6 +91,8 @@ void soc_mp_init(void)
 
 	/* Set the core 0 active */
 	soc_cpus_active[0] = true;
+	g_key_read_holder = INTEL_ADSP_ACE15_MAGIC_KEY;
+	sys_cache_data_flush_range(&g_key_read_holder, sizeof(g_key_read_holder));
 }
 
 #ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE