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soc: xtensa: intel_adsp: Refine magic key initialization for ACE 1.5 #76

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tmleman
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@tmleman tmleman commented Feb 7, 2024

Improve the initialization process for setting the magic key in ACE 1.5.

This update modifies the way the magic key is written to the global variable:

  • Utilizes a volatile pointer to ensure the key is directly written to the intended memory location.
  • Ensures the cache is flushed after the key is set to guarantee consistency between the cache and main memory.

Improve the initialization process for setting the magic key in ACE 1.5.

This update modifies the way the magic key is written to the global
variable:
- Utilizes a volatile pointer to ensure the key is directly written to
  the intended memory location.
- Ensures the cache is flushed after the key is set to guarantee
  consistency between the cache and main memory.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
@tmleman tmleman force-pushed the topic/sof/intel/mtl/drop/stable/007/hst_domain_pg_hotfix branch from 9992899 to ac47c2f Compare February 7, 2024 11:13
@tmleman tmleman closed this Feb 7, 2024
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(Sorry, didn't realize you had closed this until I was finished typing up the review; posting anyway)

First: can we not push development patches into a "drop-stable" branch ever again? Stuff needs to be validated on main first. Please. :)

Second: g_key_read_holder is a global variable, which is uncached already. I don't see how this was wrong to begin with? What was the problem you were having?

volatile uint32_t *key_write_ptr = z_soc_cached_ptr(&g_key_read_holder);

*key_write_ptr = INTEL_ADSP_ACE15_MAGIC_KEY;
sys_cache_data_flush_range(key_write_ptr, sizeof(g_key_read_holder));
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If you want to write through the cache, use z_soc_uncached_ptr(). No need to pollute a cache line.

Also the volatile here is needless. You can use volatile to control compiler[1] re-ordering or removal of a memory access you want to happen. But no compiler is allowed to skip it entirely, if you write to a global variable it will be written.

[1] But not hardware! A really common mistake is trying to use volatile where you need a memory barrier instead. Obviously this is xtensa here, which is an in-order CPU. But just in general you should be really wary of volatile; it's probably not making the promises you want.

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2 participants