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[ptl-001-drop-stable] intel_adsp: clk: Configure correct cardinal clock divider for ACE3.0 #81

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Aug 14, 2024
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[ptl-001-drop-stable] intel_adsp: clk: Configure correct cardinal clock divider for ACE3.0 #81

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3 changes: 3 additions & 0 deletions soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h
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Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,9 @@ struct ace_dfpmccu {

#define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */

#define ACE_CRODIV_CARCDS_MASK GENMASK(7, 0)
#define ACE_CRODIV_CARCDS(x) ((x) & ACE_CRODIV_CARCDS_MASK)

#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)

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5 changes: 5 additions & 0 deletions soc/intel/intel_adsp/common/clk.c
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Expand Up @@ -96,6 +96,11 @@ void adsp_clock_init(void)
} else {
platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL;
}
#if CONFIG_SOC_INTEL_ACE30_PTL
/* Set the Cardinal clock divider to 18 to get 24.576MHz */
ACE_DfPMCCU.dfcrodiv &= ACE_CRODIV_CARCDS_MASK;
ACE_DfPMCCU.dfcrodiv |= ACE_CRODIV_CARCDS(0x12);
#endif
#else
CAVS_SHIM.clkctl |= CAVS_CLKCTL_WOVCRO;
if (CAVS_SHIM.clkctl & CAVS_CLKCTL_WOVCRO) {
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