Smmcpu platform hook Before MMI Handler #6183
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This patch does not impact functionality. It aims to clarify the synchronization flow between the BSP and APs to enhance code readability and understanding: Steps tianocore#6 and tianocore#11 are the basic synchronization requirements for all cases. Steps tianocore#1 is additional requirements if the MmCpuSyncModeTradition mode is selected. Steps tianocore#1, tianocore#2, tianocore#3, tianocore#4, tianocore#5, tianocore#7, tianocore#8, tianocore#9, and tianocore#10 are additional requirements if the system needs to configure the MTRR. Steps tianocore#9 and tianocore#10 are additional requirements if the system needs to support the mSmmDebugAgentSupport. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
This patch is to add SmmCpuPlatformHookBeforeMmiHandler interface in SmmCpuPlatformHookLib. The new API can be used to perform the platform specific items before executing MMI Handler. For example, Intel can leverage this API to clear the pending SMI bit after all CPUs finish the sync and before the MMI handlers. If so, the the redundant SMI can be avoided after CPU exit from current SMI. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
This patch is to add SmmCpuPlatformHookBeforeMmiHandler func for OVMF. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
… func This patch is for PiSmmCpuDxeSmm driver to add one round wait/release sync for BSP and AP to perform the SMM CPU Platform Hook before executing MMI Handler: SmmCpuPlatformHookBeforeMmiHandler (). With the function, SMM CPU driver can perform the platform specific items after one round BSP and AP sync (to make sure all APs in SMI) and before the MMI handlers. After the change, steps tianocore#1 and tianocore#2 are additional requirements if the MmCpuSyncModeTradition mode is selected. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
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Description
This patch is to add SmmCpuPlatformHookBeforeMmiHandler interface in SmmCpuPlatformHookLib.
The new API can be used to perform the platform specific items before MMI Handler. For example, Intel can leverage this API to clear the pending SMI bit after all CPUs finish the sync and before the MMI handlers. If so, the the redundant SMI can be avoided after CPU exit from current SMI.
How This Was Tested
No function impact for open source.