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[SparseTIR] Sparse format/block/buffers #465

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merged 17 commits into from
Sep 4, 2021
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yzh119
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@yzh119 yzh119 commented Sep 3, 2021

Basic data structures of sparse format/block/buffers.
The python binding and methods will be landing in the next PR soon.
Currently we can develop lowering rules on top of this one.

cc @MasterJH5574

yzh119 and others added 15 commits August 4, 2021 15:17
* [TensorIR] Support for match_buffer from subregion (#8585)

Co-authored-by: Junru Shao <junrushao1994@gmail.com>
Co-authored-by: Bohan Hou <32121147+spectrometerHBH@users.noreply.github.com>
Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>
Co-authored-by: Hongyi Jin <3231950289@qq.com>
Co-authored-by: Wuwei Lin <wuwei@apache.org>
# Conflicts:
#	python/tvm/script/special_stmt.py
#	python/tvm/tir/transform/transform.py
#	src/tir/analysis/block_access_region_detector.cc
#	src/tir/analysis/buffer_access_lca_detector.cc
#	src/tir/transforms/lower_match_buffer.cc
#	tests/python/integration/test_lower.py
#	tests/python/unittest/test_tir_analysis_detect_buffer_access_lca.py
#	tests/python/unittest/test_tir_analysis_get_block_access_region.py
#	tests/python/unittest/test_tir_lower_match_buffer.py
#	tests/python/unittest/test_tir_transform_compact_buffer_region.py
#	tests/python/unittest/test_tvmscript_error_report.py

* [TIR] Fix opaque access in buffer locator pass and match_buffer in region detector (#8855)

* init

* fix

* Update src/tir/transforms/plan_update_buffer_allocation_location.cc

Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>

* Update src/tir/transforms/plan_update_buffer_allocation_location.cc

Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>

* address

Co-authored-by: Junru Shao <junrushao1994@gmail.com>
Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com>

* [TIR] GetBlockReadWriteRegion (#8875)

* [TIR] GetBlockReadWriteRegion

* Fix black issue

* Use constant reference for the interface

* Fix lint issue

* Catch the correct error class in logical layout test

Co-authored-by: Siyuan Feng <hzfengsy@vip.qq.com>
Co-authored-by: Junru Shao <junrushao1994@gmail.com>
* [WIP] Logical Layout lowering

* add intrin

* Logical inntrin lowering

* e2e demo

* LowerLogicalIntrin

* Remove num groups

* remove old demo

* rebase

* fix

* lower intrin pass
* Support nested software pipelining

* Update test_schedule_software_pipeline.py
@MasterJH5574
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Given it's an initial PR, let's get it merged directly :-)

String name;
/* length of current axis. For sparse axis, length refers to the upperbound of
* the current axis. */
PrimExpr length;
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Should it be an array of PrimExprs for dense-variable axes?

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No, length only record the maximum length.

@yzh119 yzh119 merged commit 23caab4 into tlc-pack:sparse-dev Sep 4, 2021
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4 participants