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[AArch64] Add a check for invalid default features (llvm#104435)
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This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.

There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field).

This resulted in a bug where if a feature was marked as `Implies` but
was not added to `DefaultExt`, then for `-march=base_arch+nofeat` the
Driver would consider `feat` to have never been added and therefore
would do nothing to disable it (no `-target-feature -feat` would be
added, but the backend would enable the feature by default because of
`Implies`). See
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c.

Note that the processor definitions do not respect the architecture
DefaultExts. These apply only when specifying `-march=<some architecture
version>`. So when a feature is moved from `Implies` to `DefaultExts` on
the Architecture definition, the feature needs to be added to all
processor definitions (that are based on that architecture) in order to
preserve the existing behaviour. I have checked the TRMs for many cases
(see specific commit messages) but in other cases I have just kept the
current behaviour and not tried to fix it.
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@tmatheson-arm
tmatheson-arm committed Aug 19, 2024
1 parent 6e30268 commit b523150
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12 changes: 6 additions & 6 deletions clang/test/CodeGen/aarch64-targetattr.c
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Expand Up @@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" }
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
//.
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12 changes: 12 additions & 0 deletions clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
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@@ -0,0 +1,12 @@
// Test that default features (e.g. flagm/sb/ssbs for 8.5) can be disabled via -march.

// RUN: %clang --target=aarch64 -march=armv8.5-a+noflagm+nosb+nossbs -c %s -### 2>&1 | FileCheck %s
// CHECK: "-triple" "aarch64"
// CHECK-SAME: "-target-feature" "+v8.5a"
// CHECK-SAME: "-target-feature" "-flagm"
// CHECK-SAME: "-target-feature" "-sb"
// CHECK-SAME: "-target-feature" "-ssbs"

// CHECK-NOT: "-target-feature" "+flagm"
// CHECK-NOT: "-target-feature" "+sb"
// CHECK-NOT: "-target-feature" "+ssbs"
2 changes: 1 addition & 1 deletion clang/test/Driver/arm-sb.c
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Expand Up @@ -11,6 +11,6 @@

// RUN: %clang -### -target arm-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT
// RUN: %clang -### -target aarch64-none-elf %s 2>&1 | FileCheck %s --check-prefix=ABSENT
// RUN: %clang -### -target aarch64-none-elf -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=ABSENT
// RUN: %clang -### -target aarch64-none-elf -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=NOSB
// ABSENT-NOT: "-target-feature" "+sb"
// ABSENT-NOT: "-target-feature" "-sb"
1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
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Expand Up @@ -6,7 +6,6 @@
// CHECK-NEXT: Architecture Feature(s) Description
// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
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Expand Up @@ -7,7 +7,6 @@
// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
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Expand Up @@ -7,7 +7,6 @@
// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
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Expand Up @@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
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Expand Up @@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
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Expand Up @@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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2 changes: 0 additions & 2 deletions clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
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Expand Up @@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
Expand Down Expand Up @@ -51,7 +50,6 @@
// CHECK-NEXT: FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions
// CHECK-NEXT: FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
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Expand Up @@ -5,7 +5,6 @@
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
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Expand Up @@ -5,7 +5,6 @@
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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19 changes: 9 additions & 10 deletions llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -787,27 +787,26 @@ def HasV8_2aOps : Architecture64<8, 2, "a", "v8.2a",
[HasV8_1aOps, FeaturePsUAO, FeaturePAN_RWV, FeatureRAS, FeatureCCPP],
!listconcat(HasV8_1aOps.DefaultExts, [FeatureRAS])>;
def HasV8_3aOps : Architecture64<8, 3, "a", "v8.3a",
[HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX,
FeatureComplxNum],
[HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureComplxNum],
!listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS,
FeaturePAuth, FeatureRCPC])>;
FeaturePAuth, FeatureRCPC, FeatureCCIDX])>;
def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a",
[HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM,
FeatureRCPC_IMMO, FeatureLSE2],
!listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd])>;
!listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd, FeatureDIT, FeatureFlagM])>;
def HasV8_5aOps : Architecture64<8, 5, "a", "v8.5a",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
FeatureBranchTargetId],
!listconcat(HasV8_4aOps.DefaultExts, [])>;
!listconcat(HasV8_4aOps.DefaultExts, [FeaturePredRes, FeatureSSBS, FeatureBranchTargetId, FeatureSB])>;
def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a",
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],
!listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a",
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],
!listconcat(HasV8_6aOps.DefaultExts, [])>;
!listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT])>;
def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a",
[HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],
!listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
Expand All @@ -825,7 +824,7 @@ def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",
!listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8, FeatureRME])>;
def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a",
[HasV8_7aOps, HasV9_1aOps],
!listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC])>;
!listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC, FeatureWFxT])>;
def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a",
[HasV8_8aOps, HasV9_2aOps],
!listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
Expand All @@ -842,7 +841,7 @@ def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
//v8.2
FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
//v8.3
FeatureCCIDX, FeaturePAuth, FeatureRCPC,
FeaturePAuth, FeatureRCPC,
//v8.4
FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2,
FeatureRCPC_IMMO,
Expand All @@ -853,7 +852,7 @@ def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
// For v8-R, we do not enable crypto and align with GCC that enables a more
// minimal set of optional architecture extensions.
!listconcat(
!listremove(HasV8_5aOps.DefaultExts, [FeatureLSE]),
!listremove(HasV8_5aOps.DefaultExts, [FeatureBranchTargetId, FeaturePredRes]),
[FeatureSSBS, FeatureFullFP16, FeatureFP16FML, FeatureSB]
)>;

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