This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).
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Updated
Oct 26, 2019 - SystemVerilog
This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
Graph Processing Framework that supports || OpenMP || CAPI
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