GitHub - MinhTran0911/Simple_CPU_DE10: Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA

MinhTran0911 / Simple_CPU_DE10 Public

Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Modelsim		Modelsim
Quartus		Quartus
.gitattributes		.gitattributes
ALU_Operation_Set.png		ALU_Operation_Set.png
Control_Unit_State_Transition_Diagram.jpg		Control_Unit_State_Transition_Diagram.jpg
Instruction_Set.png		Instruction_Set.png
Simple_CPU_Final_Block_Diagram.jpg		Simple_CPU_Final_Block_Diagram.jpg