ZipCPU / openarty Star 122 Code Issues Pull requests An Open Source configuration of the Arty platform fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus Updated Jan 17, 2024 Verilog
Sea-n / NCTU-109A-DLab Star 6 Code Issues Pull requests 109 Autumn - Digital Circuit Lab homework verilog nctu arty Updated Mar 29, 2021 Verilog
ovpanait / fpga-zynq Star 4 Code Issues Pull requests HDL + Linux on Arty Z7-20 fpga zynq bitcoin verilog arty Updated Oct 20, 2019 Verilog
2uger / tiny_soc Star 1 Code Issues Pull requests Simple implementation of SOC around PicoRV32 soft core. verilog xilinx hdl soc picorv32 verilator arty Updated May 21, 2024 Verilog
kisek / fpga_arty_a7_dram Star 0 Code Issues Pull requests This is a DDR3 SDRAM (MT41K128M16JT-125) sample project for Arty A7-35T FPGA board. fpga arty Updated Nov 2, 2024 Verilog
MatthieuMichon / picorv32 Star 0 Code Issues Pull requests PicoRV32 - A Size-Optimized RISC-V CPU fpga verilog risc-v arty Updated Jun 10, 2020 Verilog