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All 13 VHDL 3 Verilog 3 C 2 Tcl 2 Python 1 TeX 1

aryan-programmer / axi_stream_array_sum_microblaze

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A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
  • Updated Dec 3, 2023
  • C

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