#
axi-lite
Here are 13 public repositories matching this topic...
Designing means to communicate as an SPI master, being a part of AXI interface
-
Updated
Sep 14, 2023 - Verilog
Registers bank with Axi-Lite interface
-
Updated
Oct 22, 2022 - VHDL
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
-
Updated
Feb 20, 2023 - C
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped
-
Updated
Nov 21, 2023 - TeX
🏄 Custom IP for vector operations
zynq vector vhdl vivado hardware-designs hdl custom-ip fpga-accelerator axi vitis axi-lite vector-operation vector-ops vector-operations
-
Updated
Aug 31, 2024 - VHDL
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
-
Updated
Dec 3, 2023 - C
an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite
-
Updated
Jul 19, 2023 - Verilog
Improve this page
Add a description, image, and links to the axi-lite topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the axi-lite topic, visit your repo's landing page and select "manage topics."