Digital logic design tool and simulator

A FPGA friendly 32 bit RISC-V CPU implementation

VHDL 2008/93/87 simulator

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Scala based HDL

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Haskell to VHDL/Verilog/SystemVerilog compiler

Package manager and build abstraction tool for FPGA/ASIC development

Hardware Description Languages

VUnit is a unit testing framework for VHDL/SystemVerilog

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

A tiny Open POWER ISA softcore written in VHDL 2008

An abstraction library for interfacing EDA tools

VHDL compiler and simulator

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

A List of Free and Open Source Hardware Verification Tools and Frameworks

Implementation of a Tensor Processing Unit for embedded systems and the IoT.