Minimal Application based on Network Development Kit (NDK) for FPGA cards

System Verilog BootCamp

BASYS 3 - PONG GAME

learn the combinational and sequential logic circuit.

A project to implement a delayed feedback reservoir on the bladeRF 2.0 micro software defined radio (SDR) FPGA.

Counter that counts even numbers is created using a chain of eight D flip-flops. An OOP-based test bench and a package is developed to verify the counter's functionality as a black box and compare its output against the expected even number sequence. The design was implemented in two approaches i.e, asynchronous and synchronous structures.

VHDL implementation of VGA controller. Implemented on Zybo Zynq-7000 board which uses switches to change output color.

Vector ASIP for the application of filters to an image 🖼️

This project simules the basic functions of PIC16F84a.

A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).

Rešenja zadataka sa vežbi iz predmeta "Projektovanje namenskih računarskih struktura 2"

Tea Encryption for ECE 4304 VHDL Design Project

A single SystemVerilog package with both classes of half as well as full adder is created and tested using the testbench

An 8-bit counter that counts from 0 to 255 when it is enabled and parallelly loaded. Structural approach is used here and treated as a black box and is verified using OOP based testbench.