cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Package manager and build abstraction tool for FPGA/ASIC development

An abstraction library for interfacing EDA tools

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Repurposing existing HDL tools to help writing better code

Style guide enforcement for VHDL

HDL symbol generator

Streaming based VHDL parser.

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

An abstract language model of VHDL written in Python.

A package for Sublime Text that aids coding in the VHDL language.

An open-source HDL register code generator fast enough to run in real time.

Cross EDA Abstraction and Automation

hardware library for hwt (= ipcore repo)

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

LLVM based HLS library for HWToolkit (hardware devel. toolkit)