一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Connectal is a framework for software-driven hardware development.

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

P4-14/16 Bluespec Compiler

Altera JTAG UART wrapper for Bluespec

RISC-V BSV Specification

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

Yosys plugin for synthesis of Bluespec code

Bluespec System Verilog language extension for Visual Studio Code

Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.

Simple MIPS µC for educational purposes

Six stage RISC-V processor supporting the RV32I instruction set

Bluespec SystemVerilog extension for VS Code

Altera JTAG Source/Probe wrapper for Bluespec

Domain Specific Hardware Accelerators - VLSI CAD Project

Forth CPU J1 in Bluespec SystemVerilog (BSV)

Bluespec SystemVerilog language definition for the LaTeX listings package

Repository for various experiments done during Aug'21 to Mar'21 related to Side-channel-analysis of Shakti's AES accelerators

Implementation of proposed RISC-V xbitmanip instructions in BlueSpec

Hardware implementation of Lightweight Cryptography candidates in Bluespec SystemVerilog.