This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Electrical Components Tolerance Analysis Using Matlab
Electronics laboratories: I) Active filters and oscillators; II) Digital-analog converter DAC; III) Adaptive filters.
Code for designing sigma delta modulator loop filters with optimal properties.
Add a description, image, and links to the dac topic page so that developers can more easily learn about it.
To associate your repository with the dac topic, visit your repo's landing page and select "manage topics."