University of Antioquia. Digital Electronics. Restricted access system
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Updated
Dec 27, 2021 - C
University of Antioquia. Digital Electronics. Restricted access system
Designing of digital circuits based on problems in digital electronics, implemented in logic.ly simulator
University of Antioquia. Digital Electronics. Sequential circuits using flip flops
basic simulations of digital electronics using vhdl
Z80 retrocomputing project
Digital Electronics Course Project
A Digital Electronic Circuit Project and a non coding project.
This is the collection of Schematics of various digital electronics elements, verilog codes and test benches of different operation and circuits
University of Antioquia. Digital Electronics. Input Capture
4 bit up down counter counts from 0000 to 1111 if control input is set HIGH ,else it would count from 1111 to 0000. it can be build by cascading 4 nos of D flipflops with a mux at the input node to choose between UP/DOWN
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…
Contains simuations under Digital Electronics domain. HDL, VHDL based simulation results of various digital circuit blocks.
Here i develop virtual computer machine starting from Nand gates and finishing at implementing working Tetris game.
Testing methodologies on circuits for reliability
University of Antioquia. Digital Electronics. Sequential circuits using flip flops
VHDL, FPGA, Fron nand to tretris,
Design and construction of a wire guided delivery robot
8-bit CPU emulator for running simple ASSEMBLY code, final project for the 'Management and Analysis of Physics Dataset (MOD. A)' course.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs …
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