OpenSource GPU, in Verilog, loosely based on RISC-V ISA

A Framework for Design and Verification of Image Processing Applications using UVM

Bitmap Processing Library & AXI-Stream Video Image VIP

APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS

An open source, parameterized SystemVerilog digital hardware IP library

Verilog Hardware Design of Ascon v1.2

Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

A synthesizable simplified MIPS written in System Verilog

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.

This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language

This is the hardware description of the OpenTPU Project. This simulator allows anyoneto test performance of tpu on their own computer and explore hardware acceleration

Simple Single Bus RISCV Processor

The final product is amazing - a small and simple RISC-V processor that I implemented myself. The assignments are gradual and each stage makes use of the tools I have acquired so far.