Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA
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Updated
Mar 29, 2018 - VHDL
Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA
Multi-level second-order (Silva Steensgaard Structure) delta-sigma modulator
IIR audio filter in Verilog, running on Zedboard. Fractional integer coefficients.
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