HF-RISC SoC
SUTD 2020 50.002 Computation Structures Code Dump
Multi-Threaded Simulation of Process Switching in Operating System.
A final year undergraduate major project. (Dec 2019 - Mar 2020)
Full graphical instruction-level emulator for the CHIP-8 Instruction Set Architecture
c assembler & data path simulator implementing the LC-2200 ISA.
My attempt at a CPU simulator
A real time computing machine
a small, fast and flexible assembler for risc-v assembly languange. currently it fully supports all the unpriviledged instructions of RV32M Instrution set
6502 virtual machine written in C
Advanced computer architectures and programming; memory, memory management and cache organizations, parallel processing, graphical processor units for general programming.
A simple CPU architecture specification based on AArch64 and with a little x86 inspiration. Additionally, a C implementation of this architecture and an assembler written in Python.
A real time computing machine
A custom CPU implemented in 74-series logic
A multi-threaded simulation of the process switching mechanism in operating systems. This was my project in the "CSC 340: Operating Systems" course at Ahmedabad University.
Implements a datapath which is capable of executing a subset of the Motorola HC08 instruction set on a Field Programmable Gate Array (FPGA).
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