3-stage RV32IMACZb* processor with debug

Easy-to-use JTAG TAP and Debug Controller core written in Verilog

Python script for controlling the debug-jtag port of riscv cores

Tutorial on how to integrate custom JTAG functionality into existing tools

jtag tap_controller_fsm Verilog code

SPM with DFT structure automatically injected by Fault

Testing methodologies on circuits for reliability