Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
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Updated
Oct 8, 2020 - SystemVerilog
Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
RISC-V five stage pipline CPU
Final project for the class "Digital Design with Verilog and SystemVerilog"
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