basic implementation of logic structures using verilog (revising github)
registers
pipo
d-flipflop
full-adder
sipo
sequence-detector
siso
piso
verilog-testbenches
synchronous-counter
priority-encoder
jk-flipflop
t-flipflop
sr-flip-flop
full-subtractor
half-subtractor
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Updated
Feb 29, 2024 - Verilog