[WIP] Dockerize Synopsys/Cadence EDA tools
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Updated
Mar 29, 2019 - Dockerfile
[WIP] Dockerize Synopsys/Cadence EDA tools
This is a tutorial on standard digital design flow
embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC
A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
🌟 Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
Technology file parser in Rust
Example of a full DC synthesis script for a simple design
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
Synopsys Security Plugin provides functionality for performing Security Scan with Black Duck, Coverity and Polaris.
Typical project for Synopsys DC Compiler
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
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