SystemRDL 2.0 language compiler front-end

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Control and status register code generator toolchain

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Generate address space documentation HTML from compiled SystemRDL input

Import and export IP-XACT XML register models

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

C++ 17 Hardware abstraction layer generator from systemrdl

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

This repository is for DEDA class in 2017.