Designed a Neural Network Generator using C++ and System Verilog
-
Updated
May 21, 2017 - C++
Designed a Neural Network Generator using C++ and System Verilog
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
A flexible hardware module written in SystemVerilog which implements the Mersene twister (using a 32-bit word length). A simulation and a test bench written in SystemC, which uses Verilator were created in order to verify the correctness and to measure performance of the hardware module.
A verilator testbench framework.
What's that weird looking CPU?
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
Running verilog on hardware, desktop and the web
A library and command-line tool for querying a Verilog netlist.
UML-JTracing是基于C++20实现,针对于芯片领域常用C++和SystemVerilog两种编程语言自动进行高鲁棒性的词法解析和常见语法分析和语义分析,生成可靠Abstract Syntax Tree,并提供Parser解析过程信息、报错信息和变量表等解析信息,通过自定义数据结构对解析过程进行格式化存储,最终将利用Python实现的UML智能生成器检测到结构化后的解析信息,通过加载解析信息进行自动绘制目标源代码的UML时序图
A codebase for learning effective use of verilator
80186 compatible SystemVerilog CPU core and FPGA reference design
design-and-verification-of-MCDF-phase4
Examples of SystemC from the High-Level Systems Design course of the Master's Degree in Electronics at the Costa Rica Institute of Technology.
Add a description, image, and links to the systemverilog topic page so that developers can more easily learn about it.
To associate your repository with the systemverilog topic, visit your repo's landing page and select "manage topics."