A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
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Updated
Sep 9, 2024 - Tcl
A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.
A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.
This project focuses on implementing a VGA interface and a screensaver for the Basys 3 FPGA Board. It involves generating VGA signals to display images stored in ROM, showcasing how to control and synchronize video output. The project culminates in programming the FPGA to display a functional screensaver on a VGA monitor.
A WIP RISC-V CPU implementation. Right now I'm working on implementing RV32I.
A Tcl-Library for scripted HDL generation
Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board
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