Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

A modern and open-source cross-platform software for chips reverse engineering.

Open source software for chip reverse engineering.

A VHDL frontend for Yosys

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Official repsitory of Qfsm, a graphical Finite State Machine (FSM) designer

A library of VHDL components for Neural Networks

Creates a .SVG symbol from a VHDL entity. Colors and some other properties can be adjusted.

VHDL Diagram Editor

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

Wallace and Dadda tree multiplier generator in vhdl and verilog

Compiler for generating fixed-point logic using VHDL

A custom 32-bit architecture, microcontroller, retro console, and software suite

A simple driver for RGB Led Panels of different sizes

Value Change Dump (VCD) File parser

Random number generators based on chaotic functions

A library to translate strings between common EDA naming conventions.

Work examples