Skip to content

Actions: trabucayre/litex

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
92 workflow runs
92 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

build/vhd2v_converter: allows using an instance instead of entity_nam… ci #169: Commit a6845a7 pushed by trabucayre
December 19, 2024 14:21 37m 55s litex_vhd2vconvert_instance
litex_vhd2vconvert_instance
December 19, 2024 14:21 37m 55s
build/xilinx/platform: added xilinx_us_special_overrides for xczu dev… ci #168: Commit 95e7640 pushed by trabucayre
December 12, 2024 10:47 38m 43s xczu_special_overrides
xczu_special_overrides
December 12, 2024 10:47 38m 43s
build/lattice/common.py: added Tristate support for ECP5 when build w… ci #167: Commit 211ce59 pushed by trabucayre
November 17, 2024 10:32 38m 52s ecp5_diamond_tristate
ecp5_diamond_tristate
November 17, 2024 10:32 38m 52s
build/vhd2v_converter.py: allows users to pass a list of libraries fi… ci #166: Commit f731b36 pushed by trabucayre
November 9, 2024 06:55 38m 26s vhd2vconverter_libraries
vhd2vconverter_libraries
November 9, 2024 06:55 38m 26s
litex/build/lattice/diamond, platform: allows users to add custom sdc… ci #165: Commit 47e8b02 pushed by trabucayre
November 4, 2024 11:42 38m 22s toolchain_diamond_sdc
toolchain_diamond_sdc
November 4, 2024 11:42 38m 22s
litex/soc/cores/jtag.py: lattice target: INIT -> init (otherwise fail… ci #164: Commit 06f9f97 pushed by trabucayre
October 16, 2024 11:47 41m 41s build_diamond_addition
build_diamond_addition
October 16, 2024 11:47 41m 41s
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with opt… ci #163: Commit ddb8d16 pushed by trabucayre
October 9, 2024 14:14 43m 23s zynqmp_ethernet_sgmii
zynqmp_ethernet_sgmii
October 9, 2024 14:14 43m 23s
build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK… ci #162: Commit f1e1f35 pushed by trabucayre
September 19, 2024 07:14 27m 9s efinix_clkinput_signal
efinix_clkinput_signal
September 19, 2024 07:14 27m 9s
build/xilinx/platform.py: added xc7s to the list of device supporting… ci #161: Commit e072156 pushed by trabucayre
September 19, 2024 04:49 40m 45s xc7s_jtag
xc7s_jtag
September 19, 2024 04:49 40m 45s
build/efinix/common.py: ClkInput: added ClockSignal support ci #160: Commit e81bd16 pushed by trabucayre
September 18, 2024 13:25 41m 8s efinix_clkinput_signal
efinix_clkinput_signal
September 18, 2024 13:25 41m 8s
soc/cores/clock/efinix.py: create_clkin try to extract input_signal f… ci #159: Commit d1aec39 pushed by trabucayre
September 10, 2024 14:34 25m 52s efinix_rework_primitives
efinix_rework_primitives
September 10, 2024 14:34 25m 52s
build/efinix/ifacewriter.py: LVDS: when clk is a clockSignal uses pla… ci #158: Commit 0d5fb36 pushed by trabucayre
September 10, 2024 13:44 25m 56s efinix_rework_primitives
efinix_rework_primitives
September 10, 2024 13:44 25m 56s
build/efinix/common.py: ClkOutput now must receive a ClockSignal ci #157: Commit 8e1bb6b pushed by trabucayre
September 10, 2024 09:26 25m 28s efinix_rework_primitives
efinix_rework_primitives
September 10, 2024 09:26 25m 28s
soc/cores/clock/efinix.py: uses self.name for clk_name, remove add_pe… ci #156: Commit b3a7ceb pushed by trabucayre
September 10, 2024 09:08 25m 32s efinix_rework_primitives
efinix_rework_primitives
September 10, 2024 09:08 25m 32s
soc/cores/clock/efinix.py: added pll+id in clkout name ci #155: Commit 276aa6e pushed by trabucayre
September 10, 2024 06:16 40m 25s efinix_rework_primitives
efinix_rework_primitives
September 10, 2024 06:16 40m 25s
build/altera/common: added special AsyncResetSynchronizer based on al… ci #154: Commit d021500 pushed by trabucayre
September 3, 2024 15:47 40m 28s altera_agilex5_asyncresetsynchronizer
altera_agilex5_asyncresetsynchronizer
September 3, 2024 15:47 40m 28s
build/gowin/apicula: only append _packer_opts with known use_xxx (dro… ci #153: Commit babe233 pushed by trabucayre
September 1, 2024 06:57 40m 56s gowin_apicula_fix
gowin_apicula_fix
September 1, 2024 06:57 40m 56s
build/colognechip/colognechip.py: simplify constrains file with the n… ci #152: Commit 0fcc27f pushed by trabucayre
August 24, 2024 09:23 43m 59s colognechip_improve
colognechip_improve
August 24, 2024 09:23 43m 59s
build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora… ci #151: Commit 3cd8209 pushed by trabucayre
August 4, 2024 06:42 40m 26s gowin_build_gw5a_primitives
gowin_build_gw5a_primitives
August 4, 2024 06:42 40m 26s
build/gowin/common.py: re-add tristate impl and SDRxxx (required for … ci #150: Commit 74c9b4c pushed by trabucayre
August 4, 2024 06:41 40m 13s gowin_build_gw5a_primitives
gowin_build_gw5a_primitives
August 4, 2024 06:41 40m 13s
build/altera/common.py: implement SDRTristate for Agilex5 family ci #149: Commit 1f6673c pushed by trabucayre
July 30, 2024 13:38 38m 32s altera_agilex5_sdrtristate_special
altera_agilex5_sdrtristate_special
July 30, 2024 13:38 38m 32s
build/altera/common.py: implement SDRTristate for Agilex5 family ci #148: Commit 1e24eda pushed by trabucayre
July 30, 2024 13:35 41m 6s altera_agilex5_sdrtristate_special
altera_agilex5_sdrtristate_special
July 30, 2024 13:35 41m 6s
build/altera/common,platform: added ddrinput/ddrout primitives ci #147: Commit dc04949 pushed by trabucayre
July 25, 2024 11:13 41m 43s altera_agilex5_ddr_special
altera_agilex5_ddr_special
July 25, 2024 11:13 41m 43s
build/efinix: added argument to change synthesis options configurations ci #146: Commit ec1528f pushed by trabucayre
July 8, 2024 13:59 40m 23s efinix_args_opts
efinix_args_opts
July 8, 2024 13:59 40m 23s
build/altera/quartus.py: added support for ips other than QSYS_FILE ci #145: Commit 9fd6397 pushed by trabucayre
July 4, 2024 06:53 40m 13s update_altera_build
update_altera_build
July 4, 2024 06:53 40m 13s