Is, or will be, the Xilinx XC9536XL supported? #104

jduraes · 2021-08-10T16:07:51Z

Hello,

I don't see the Xilinx XC9536XL as one of the supported devices today - so I'm guess the first answer is, "no, not supported". The follow-up question is, will it? When/how, please? :-)

Just to confirm my understanding of the error message below is right, would this be a resulting message for an unsupported device? I'm using a Tigard board to program an Interface 1bis that has the Xilinx on board.

$ openFPGALoader -c tigard IF1bis4bPld.jed
write to ram
Jtag frequency : requested 6.00MHz -> real 6.00MHz
JTAG init failed with: Unknown device with IDCODE: 0x59602093

Many thanks.

trabucayre · 2021-08-14T13:05:50Z

It's true xc9 aren't currently supported. I have one but jed needs to be improved to be less lattice only.
Since you are interested by this support I will working on that.

jduraes · 2021-08-14T13:08:02Z

Thanks very much. Let me know if there is anything you'd like me to test.

trabucayre · 2021-08-18T13:58:11Z

Hi.
I've added support for all XC95 CPLD.
Could you try it?
Thanks

jduraes · 2021-08-19T08:36:24Z

Thank you. Will do it shortly and report back.

jduraes · 2021-08-19T08:50:57Z

I'm guessing, it might have worked!

$ openFPGALoader -c tigard IF1bis4bPld.jed --verify
write to ram
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file Error: wrong checksum
DONE
Jtag frequency : requested 1.00MHz   -> real 1.00MHz  
Erase flash DONE
Write Flash: [==================================================] 100.00%
Done
Read Flash: [==================================================] 100.00%
Done
Verify Flash: [==================================================] 100.00%
Done

Question: that "error" regarding a wrong checksum on the file I've used, is that a big issue? The file wasn't created by me, so I'm not sure what that means. It appears to have programmed the CPLD successfully nonetheless - although I cannot confirm it just yet.

Before I can test the device I need to program two other MCUs on the device, so I'll do that next and give the final confirmation later. Many thanks again.

jduraes · 2021-08-19T08:59:23Z

Just for completeness:

$ openFPGALoader -c tigard --detect
write to ram
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
index 0:
	idcode 0x59602093
	manufacturer xilinx
	family xc9500xl
	model  xc9536xl
	irlength 8

trabucayre · 2021-08-19T12:47:44Z

Could you share your jed (not by copy/paste here). It's weird I've build a jed for the same device as you and the checksum is correctly computed...
Thanks

jduraes · 2021-08-19T16:41:20Z

Sure; here it is.
IF1bis4cPld.zip

trabucayre · 2021-08-20T07:21:38Z

Thanks.
I've reproduce your issue and found my error. Now I need to check now for lattice's jed too and ASAP when I'm sure this not introduce regression, I push the fix.

jduraes · 2021-08-20T07:46:09Z

I see... So do you think the programming of that jed on my device did not complete successfully? It verified OK, but I haven't yet been able to program one of the MCUs on this board to confirm that all is working properly. Thanks for following up.

…

On Fri, 20 Aug 2021, 08:21 Gwenhael Goavec-Merou, ***@***.***> wrote: Thanks. I've reproduce your issue and found my error. Now I need to check now for lattice's jed too and ASAP when I'm sure this not introduce regression, I push the fix. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#104 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABNWZHXPVG5735BMHBV7B6TT5X7A3ANCNFSM5B4O6VRA> .

trabucayre · 2021-08-20T07:59:05Z

I have pushed fix for checksum. The error is about the way to compute checksum.
This check is, with xc9500xl, only to verify file is not corrupted. Your CPLD has been correctly programmed.

jduraes · 2021-08-20T12:03:41Z

Nice one. Thank you for all your help.

trabucayre · 2021-08-23T14:45:44Z

It's okay for you. Can I close this issue?

jduraes · 2021-08-23T14:48:17Z

I cannot yet confirm if the CPLD is working as expected, as I suspect I have an issue in my device elsewhere, but writing/verifying the FPGA appears to happen ok. So I have to assume that it is working correctly. I also no longer get that checksum error. Yes, please close the issue.

tcmichals · 2022-07-15T14:59:35Z

I'm also trying to use a xc9536xl and did the following:
./openFPGALoader -c digilent_hs3 --detect
Jtag frequency : requested 6.00MHz -> real 6.00MHz
index 0:
idcode 0x9602093
manufacturer xilinx
family xc9500xl
model xc9536xl
irlength 8

Then do a:
./openFPGALoader -c digilent_hs3 /home/tcmichals/Downloads/G_MAIN.jed --verify
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Erase flash DONE
Write Flash: [==================================================] 100.00%
Done
Jtag frequency : requested 1.00MHz -> real 1.00MHz
Read Flash: [==================================================] 100.00%
Done
Verify Flash: [==================================================] 100.00%
Fail
Error: wrong value: read 00 instead of 40

i will also try and debug this, will reprogram using a working tool then attempt to just verify and see what that is not working first.

trabucayre · 2022-07-15T19:23:59Z

I will retry this week-end. But could you share your jed file?
Thanks!

tcmichals · 2022-07-15T20:24:11Z

Yes, here it is.
G_MAIN.zip

trabucayre · 2022-07-16T08:12:19Z

Thanks for the bitstream.
I have retried to flash my board: it's works. But it's an xc9572xl and unfortunately it's a bit hard to find your model (or at least with short delivery delays).
But before: a check between 1532.bsd and the 36 model must be done, 36 and 72 have not exactly the same sequence.

tcmichals · 2022-07-19T13:05:23Z

OK, what is the best way to debug this issue?

trabucayre · 2022-07-19T17:03:43Z

I have ordered one board but I have to wait for 2 or 3 weeks.
When you flash a bitstream without verify write the new bitstream is not working? True?
The first thing is to check flow_program behaviour to verify if everything is ok for this specific model.
I have started to do that.
In some points there is delays based on clock frequency: maybe values are too short.

tcmichals · 2022-07-19T17:37:03Z

When you flash a bitstream without verify write the new bitstream is not working? True?
Correct, it is not working.

tcmichals · 2022-07-21T22:21:05Z

FYI: xc3sprog does work with this device.

./xc3sprog -c jtaghs2 ~/Downloads/G_MAIN.jed -v
TIM XC3SPROG (c) 2004-2011 xc3sprog project $Rev: 774 $ OS: Linux
Free software: If you contribute nothing, expect nothing!
Feedback on success/failure/enhancement requests:
http://sourceforge.net/mail/?group_id=170565
Check Sourceforge for updates:
http://sourceforge.net/projects/xc3sprog/develop

Using built-in device list
Using built-in cable list
Cable jtaghs2 type ftdi VID 0x0403 PID 0x6014 Desc "Digilent USB Device" dbus data e8 enable eb cbus data 00 data 60
Using Libftdi, Using JTAG frequency 6.000 MHz from undivided clock
JTAG chainpos: 0 Device IDCODE = 0x59602093 Desc: XC9536XL
Device is not blank
Programming Sector 107.
Programming time 10909.4 ms
Verify Sector 107
Success! Verify time 137.5 ms
USB transactions: Write 1954 read 1734 retries 461

trabucayre · 2022-07-22T05:48:23Z

Maybe it's a good starting point to check if xc9536xl has some small specificities I have lost.

)

trabucayre · 2022-08-04T06:26:03Z

I have received my xc9536XL board and fixed issue: one of delays was too short.
Repo is now updated: could you check in your side to confirm the fix is working (or not).
Thanks.

tcmichals · 2022-08-04T20:01:27Z

openFPGALoader v0.9.0

Is working.

trabucayre · 2022-09-03T22:51:20Z

Thanks!
@jduraes is it ok for you too? Can I close this issue?

jduraes · 2022-09-04T08:25:56Z

I do not have the means to test it right now. When I do in the future, I'll circle back into this thread if it doesn't work. Go ahead and close it for now. Oh and thanks for asking.

…

On Sat, 3 Sept 2022, 23:51 Gwenhael Goavec-Merou, ***@***.***> wrote: Thanks! @jduraes <https://github.com/jduraes> is it ok for you too? Can I close this issue? — Reply to this email directly, view it on GitHub <#104 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABNWZHWCIUVNVDGJVQ6UBR3V4PI7HANCNFSM5B4O6VRA> . You are receiving this because you were mentioned.Message ID: ***@***.***>

trabucayre · 2022-09-04T09:19:09Z

Thanks.
Don't hesitate to reopen or create a new issue if something goes wrong!

jduraes changed the title ~~Is, or will be, the Xilinx XC9536XL10 supported?~~ Is, or will be, the Xilinx XC9536XL supported? Aug 10, 2021

trabucayre added a commit that referenced this issue Aug 4, 2022

xilinx: flow_program/xc95: increase delay and use getClkFreq (issue #104

c6d79ec

)

trabucayre closed this as completed Sep 4, 2022

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Is, or will be, the Xilinx XC9536XL supported? #104

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Is, or will be, the Xilinx XC9536XL supported? #104

Is, or will be, the Xilinx XC9536XL supported? #104

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