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Is it possible to have less log messages when programming the FPGA ?
$ ./cycloader -c digilent_hs3 pouet_impl1.jed try to open 403 6014 -1 -1 found 1 devices idcode 0x612bd043 funder lattice model MachXO3LF family LCMX03LF-6900C jed G0 F0 fuse checksum C5343 AA 5343 inconnu UH00000000 end area[0] 0 269056 area[1] 269056 1172224 theorical checksum 5343 -> 5343 array size 2102 IDCode : 612bd043 00 08 0f 10 displayReadReg Config Target Selection : 0 JTAG Active Done Flag ISC Enable Write Enable Read Enable SDM Enable No err flash erase 00 08 0e 10 displayReadReg Config Target Selection : 0 JTAG Active ISC Enable Write Enable Read Enable SDM Enable No err 00 08 0f 18 displayReadReg Config Target Selection : 4 JTAG Active Done Flag ISC Enable Write Enable Read Enable SDM Enable No err flash erase 00 00 0e 18 displayReadReg Config Target Selection : 4 JTAG Active ISC Enable Write Enable Read Enable No err Writing: [==================================================] 100.00% Done 00 00 0e 18 displayReadReg Config Target Selection : 4 JTAG Active ISC Enable Write Enable Read Enable No err Verifying: [==================================================] 100.00% Done 00 00 0e 18 displayReadReg Config Target Selection : 4 JTAG Active ISC Enable Write Enable Read Enable No err 00 00 0e 18 displayReadReg Config Target Selection : 4 JTAG Active ISC Enable Write Enable Read Enable No err 00 00 00 00 00 00 00 00 0600 boot mode : Single Boot from NVCM/Flash Master Mode SPI : disable I2c port : disable Slave SPI port : disable JTAG port : enable DONE : disable INITN : disable PROGRAMN : enable My_ASSP : disable Password (Flash Protect Key) Protect All : Disabled Password (Flash Protect Key) Protect : Disabled 00 00 0e 18 displayReadReg Config Target Selection : 4 JTAG Active ISC Enable Write Enable Read Enable No err 00 08 0f 18 displayReadReg Config Target Selection : 4 JTAG Active Done Flag ISC Enable Write Enable Read Enable SDM Enable No err 00 08 01 00 displayReadReg Config Target Selection : 0 Done Flag SDM Enable No err 00 08 01 00 displayReadReg Config Target Selection : 0 Done Flag SDM Enable No err
The text was updated successfully, but these errors were encountered:
Fixed with 8d0bfeb thanks
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Add CH347T(mode trabucayre#3) JTAG cable
bc2f9d5
Add WCH CH347T(mode #3) JTAG cable
0fc8ba1
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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Is it possible to have less log messages when programming the FPGA ?
The text was updated successfully, but these errors were encountered: