Skip to content

v0.12.0 release
Compare
Choose a tag to compare
@trabucayre trabucayre released this 09 Mar 09:28
· 131 commits to master since this release
v0.12.0
a1fd711

Evolution summary:

core

new

  • CMake: bump the minimal required version to 3.5
  • Add WebAssembly support.
  • ftdiJtagMPSSE,jtag,jtagInterface: allows to force read/write edge configuration (useful to mimic SPI through JTAG)
  • ftdiJtagMPSSE,jtagInterface: {set|get}{Read|Write}Edge signature
  • Add user device list for non-fpga JTAG devices

update

  • jtag: rework detectChain: try unmasked idcode first
  • jtag: update JTAG chain detect
  • jtag: move JTAG chain bit init to device_select()

fix

  • jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' (fix #189 and #133
  • jtag: fix state machine (issue introduce by commit 9e91c3)
  • make IDCODE unsigned
  • macos workflow
  • drop mingw w32

board

new

  • Gaisler gr740-mini
  • QMTECH cyclone10 LP starter kit (10CL016YU484C8G)
  • @lambdaconcept ecpix5_r03 (ft4232)
  • SiPEED tang Primer 25K
  • SiPEED tang Mega 138K
  • Digilent cmoda7_15t
  • ALINX AX7102 board.
  • ALINX AX7101 board.
  • Avnet Mini-ITX
  • pynq-z1 board
  • Cern VEC_V6 Board
  • Cern VMM3 board
  • Antmicro DDR4 Tester board
  • Antmicro DDR5 Tester board
  • Antmicro LPDDR4 Tester board
  • trion_t20_bga256_jtag support
  • Xilinx KCU105 (Kintex Ultrascale xcku040)
  • AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
  • Add GD32VF103 to misc devices
  • Trenz TE0712-8 Board (XC7A200TFBG484)
  • Trenz TEC0330 board
  • Olimex GateMate A1 EVB

update

  • Lattice: nexus boards: change from CABLE_DEFAULT (i.e. 6MHz) to CABLE_MHZ(1) (i.e. 1MHz) as at 6MHz the download of bitstreams is not stable.

files

new

  • fsParser: adding GW5A-25 IDCODE
  • latticeBitParser: add support for loading Lattice (Nexus) encrypted bitstreams, by adding key and preamble of encrypted bitstreams to if statements.
  • latticeBitParser: add ECP3 VERIFY ID support (avoid to fail with bitstream)

cable

new

  • FTDI FT4232HP mapping
  • efinix jtag ft2232 variant
  • Add faulty MPSEE cmd 8E workaround

update

  • drop div_by_5 to allow 2.5MHz clock
  • Make CH347 driver faster Speed up toggleClk
  • update CH347 (#424)
  • xvc client: ensure send() entire buffer
  • xvc client: handle failed ll_write()
  • all jtag cable: no more hardcoding tdi bit with writeTMS

fix

  • DFU: fix code to accept tinyDFU implementation (where not altsettings have an DFU descriptor)
  • svf_jtag: fix -Wmismatched-new-delete delete -> delete[]

part

new

  • main: allows mcufw only mode for gowin
  • Lattice: Add all MachXO[23] part IDs
  • Lattice: improve info about "BSE Error Code" from Device Status Register
  • Lattice: machXO3: re-add partially revision
  • Gowin: add known ID codes for GW5 series
  • Gowin: add preliminary support for GW5AST-138
  • Gowin: GW5A SPI flash support
  • Gowin: Fix status register parse for GW5AST
  • Gowin: avoid multiple status register access
  • Gowin: Fix clk cycle after sending a command, don't read status register programSRAM sequence
  • Gowin: mcufw may be written without fs (but this erase all memory)
  • Gowin: detectFamily new function
  • Xilinx: add jtag->flush before sleep
  • Xilinx: Add Kintex Ultrascale+ KU3P ID-Code.
  • Xilinx: xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
  • Xilinx: XADC and DNA for Xilinx FPGA (#407)
  • Xilinx: xcku115 to parts list (#394)
  • Xilinx: Add remaining ZynqMP IDs
  • Xilinx: Add xc7k70t and small fixes for xc7k160t
  • Xilinx: Virtex 7 xc7vx330t

update

  • part: Add separator for each chip family.
  • part: Reorder families (older first, smaller first) and minor alignment cleanups.
  • part: Add separator for each vendor.
  • Altera/Intel: update idcode (same idcode for III/IV/10 LP)
  • Lattice: 0x012bc043 is for LCMXO2-4000HC
  • Lattice: restore bypass instruction in clearSRAM()
  • Lattice: spi_put: avoid loop when tx == NULL
  • Lattice: programming and add nexus boards
  • Gowin: GW5A/SPI flash: adding delay after erase flash and after SPI mode instruction. Seems fixed write error.
  • Gowin: displayReadReg update. Now GW5A field are correctly displayed
  • Gowin: Rewrite algorithms
  • Xilinx: Fix XC2 ident.

fix

  • Altera,Efinix,Gowin,Xilinx: Fix 'Flash SRAM' -> 'Load SRAM'
  • Gowin: fix flash erase for GW1NSR-4C: during shiftDR sequence TDI MUST be 0x0000
  • Gowin: writeFLASH: increase delay before CRC check (required for 9K device)
  • Gowin: try second eraseSRAM before writeSRAM. Not always working but better...
  • Gowin: GW5AST work around
  • Gowin: programFlash/writeFlash: disable previous rewrite (fix write with tangnano4k)
  • Gowin: fix gw1n external flash access
  • CologneChip: gatemate: do not call ftdi-related routines when using alternative cables
  • CologneChip: gatemate: fix configuration in jtag chains
  • CologneChip: gatemate: use more suitable change to RUN_TEST_IDLE state
  • Lattice: nexus family: REFRESH (plus config logic reset) in case of fpga in error state and add capabilities to handle the whole 64-bits status register
  • Lattice: fix bscan width and other minor things for NEXUS family
  • Lattice: fix the warning "left shift count >= width of type" shown in win32/64 builds
  • Lattice: fix bscan register initialization inside clearSRAM()
  • Lattice: correct mask for sram erase for NEXUS_FAMILY, as it is 0x00
  • Fix SRAM loading on invalid flash

spiFlash

new

  • Macronix MX25L51245G (CertusPro Versa board and gr740-mini)
  • Micron MT25/N25Q128_1_8V (Lattice Certus Versa and CertusPro eval boards) and distinguish between N25Q128 1.8V and 3V memories
  • S25FL128L flash
  • Macronix MX25L3233F used on Cmod A7-35T
  • N25Q256A

fix

  • ftdispi: add missing status_pin
  • ftdipp_mpsse: fix format-zero-length snprintf -> memset

spiOverJtag

new

  • Xilinx : xcku3p_ffva676 support.
  • Xilinx : xc7a35tfgg484 support.
  • Xilinx: xc7a15tcpg236 support
  • Xilinx: xc7k70tfbg484 support
  • Xilinx: add constr_xc7k_fbg676.xdc
  • Xilinx: Virtex6: Add spiOverJtag for Virtex6, detect xc6vlx130 and provide bitfile for xc6vlx130tff784
  • Xilinx: Virtex 7 xc7vx330tffg1157
  • Intel/Altera: cyclone10 LP 10CL016YU484C8G

update

  • compress spiOverJtag for Darwin too
  • remove obsolete xc6 directory
  • Xilinx: Update code since Virtex Ultrascale has apparently been replaced with Xilinx Ultrascale.
  • Xilinx: Rearrange for better extensibility - Use ifdef ... elsif ... `endif for better seperation
  • Xilinx: XC6SLX...L may need other pin constraints as XC6SLX... - Checked and handled for XC6Sxxx(T)fgg484

fix

  • Xilinx: fix errors on xc6slx150tfgg484
  • Xilinx: add missing xc6s_tqg144 constraint

doc

new

  • board: Avnet Mini-ITX Base Kit
  • part: Gowin GW5A serie
  • part/board: certus boards/parts entries
  • cable: FT4232HP cable/interface.

update

  • data: adding an (unused for now) SPIFlash entry

fix

  • board: fix wrong constraints link
  • board: fix efinix naming / mode

Contributors

Contributors

whitequark, hansfbaier, and 22 other contributors
Assets 5
Loading