These are the results of OpenSTA software on the above verilog codes:

This repository aims to generate timing reports of several circuits and on the path we will also learn how to write constraints(clock constraints, delay constraints, environment constraints and so on) in sdc (Synopsys design constraints) file, we will also learn how to use various modelling techniques (NLDM,ECS,CCS,etc). We then will proceed to see how process (slow, fast,typical ) affects the timing of circuits and then finally we will perform MMMC and then finish the goal of learning how to generate timing reports.

Circuit1

I used the follwing SDC constraints -

I used the following TCL script -

I got the following Min and Maxz timing reports -

FSM1

You will find the code for this in the above file. But, this is not at gate level abstraction, STA can be peformed at only gate level. So, we have to first convert this to gate level conisting of standard cells from the library. For this, we do logic synthesis (technology mapping) using the following script :

read_liberty -lib NangateOpenCellLibrary_typical.lib

read_verilog top.v

synth -top top

dfflibmap -liberty NangateOpenCellLibrary_typical.lib

abc -liberty NangateOpenCellLibrary_typical.lib
opt
share -aggressive

write_verilog -noattr top_mapped.v

I have also included Synopsys design constraints (SDC) file and set clock latency and output latency in that. These are the constraints I have set :
create_clock -name CLK -period 1000 [get_ports clk]
set_input_delay 5 -clock CLK [get_ports x]
set_output_delay 5 -clock CLK [get_ports y]

Now, the above script will create a netlist of standard cells and write it to a file named top_mmapped.v We can run sta on this file. The circuit looks like this :

To perform sta I used the following tcl script :
read_liberty NangateOpenCellLibrary_typical.lib
read_verilog top_mapped.v
link_design top
read_sdc top.sdc
report_checks -path_delay max -format full
report_checks -path_delay min -format full

I got the following timing reports on the terminal :

FSM2

Technology mapped netlist -

STA for clock period of 1000 -

Clearly, both hold and setup constraints are met.
Let us reduce the clock period in SDC file to 5 and see what happens

As you can see the hold constraint is met but the setup contraint is violated as setup slack is negative which means that the required time is lesser than the arrival time

Not just this, we can also do power estimation using OpenSTA. We have to specify input_transition and output load for all inputs and outputs in sdc file and set activity factor in tcl script and then add the command report_power to the tcl script and it will give u the power analysis as shown :

Timer

Technology mapped netlist -


STA for clock period of 5 -


Clearly, setup violation exists. To overcome this we can increase clock period
STA after increasing the clock period to 10 -


Now, both setup and hold constraints are met.
Power analysis using OpenSTA tool -


Having done this, we know that there are variations due to process parameters in the timing, what can we do to overcome this. One way is to consider a worst case but this would be pessimistic. Another way, is to perform multimode multicorner(MMMC) analysis and peform timing analysis for all corners (Process, RC parasitics). Now , let us read 3 liberty files in tcl file which are - read_liberty -
lib NangateOpenCellLibrary_typical.lib
read_liberty -lib NangateOpenCellLibrary_slow.lib
read_liberty -lib NangateOpenCellLibrary_fast.lib
We get the following results for typical -


We get the following results for slow -

As you can see the results greatly vary

Now , let us see the results for fast -


All these reports are generated at once without performing the analysis again and again, so using this method we can generate the timing reports for various processes. Clearly, fast is better than typical which is better than slow. These are NLDM (Non linear delay modelling). For accurate analysis we can also use Composite current source (CCS) and Effective current source(CCS) libraries.

Design1

Technology mapped netlist -


Area of the circuit obtained from library -


Now, let us perform MMMC on slow, typical and fast processes and see the timing reports for the above design -
Slow process -



Typical process -



Fast process -




Now , let us see if the hold and setup time of the elements changes if I change the input and clock slew. As we know the setup and hold time of elements depends on the input and clock slew, let me change input and clock slew in the sdc file and let us compare with previous result of typical library -

As you can see , the library setup time has changed slightly when i changed the sdc command from set_input_transition 0.3[get_ports i] to set_input_transition 0.6[get_ports i]. Even for such minute change in input slew, the library setup time is affected

Now let us use CCS (Composite current source - typical library) and see what changes
First let us perform tech mapping -

As expected the technology mapping remains the same as the cells are still the same , the way of calculating delay and power has changed from NLDM which was previously used


Now let us generate timing reports -
I got a lot of warning messages as OpenSTA does not support 'when' attributes, so wherever there is when attribute in the library i got a warning -

I got the following timing report after the warnings -

Edge detector

Technology mapped netlist -


Area of the circuit obtained from library -


Now, I wont be performing MMMC , that has already been demonstrated in previous examples, in this example we will be seeing how changing output capacitance affects delay and power. Also, let us change other parameters and see how those affect library setup time,library hold time, delay and power.
If i have these constraints on my sdc -
Clock period - 10 ; input delay - 5, output delay - 10; input transtion - 0.6; load - 0.2
For the above constraints let us generate timing reports -

Both setup and hold constraints are met.

And we get power as shown above. Now, let us change the transition of input that is activity factor and increase it to 0.9 from 0.6 keeping the other things constant. From theory we expect that dynamic power dissipation will increase, increasing the total power but leakage and other power dissipation should stay constant. Let us see the results -

These are as expected. Now let us keep switching activity of input port at 0.9 and change output load from 0.2 to 4 and see how it affects our power. Theoretically again leakage power will never be affected, dynamic power will go up as larger the capacitance more is the effort to switch it from one logic level to another.

Clearly, this is exactly what we expected it to be. Now let us change back the constraints to what they were originally. Now let us change the input delay to 15, we expect setup slack to be affected in a negative manner. Let us see the results -

Clearly, the setup slack has been violated.

This is the end of repository, the learning about OpenSTA is complete. After this point it is very easy to go look up their doc and read what individual command does and then use it. With this knowledge, it should be easy to generate timing reports and analyse power for various circuits.....